Reset logic in nano carrier board

Hi,

I would like to understand the reset button logic provided in the nano eval board. As per the product design guide, power supply and sequencing topic, it says that once power_en is high, nano begins to boot up and provides sys_reset as high. with sys_reset we need to make power enable for carrier board. This sys_reset is bi-directional, when this is pulled low, nano will reset and the power to carrier board will disconnect.

But my question is, when asserting sys_reset, how the nano will re-boot itself. because, once sys_reset is asserted, power_en will be in high , som will get turn off but how it re-boot? I have probed the power_en pin from SR latch output when asserting the reset pin, it remains high.

Can anyone explain me how this reset in nano eval kit works

Thanks

Hi, when SYS_RESET is triggered, the PMIC and Tegra chip will reset directly and POWER_EN status will keep high always in this process. You can refer to OEM DG of TX1 for more detail info: http://developer.nvidia.com/embedded/dlc/jetson-tx1-oem-product-design-guide