A question about RESET_OUT# Pin:
According to Jetson TX2 Product Design Guide, the RESET_OUT# pin should be held low by the carrier board, until the carrier board power rails settle to their final voltage levels.
But, there is a pull up resistor to VDD_1V8 on the Jetson TX2 module itself, pulling high that pin prior to the time that the VDD_5V0_IO_SYS power is applied to the last regulator on carrier board (APW8805 in P2597_C02 schematic. Also see Figure 7 and 8 in the Jetson TX2 Product Design Guide)
I think there is an inconsistency between two above points.
Would you please provide more details on this?
It will be held low by PGOOD.
Yes, Power Good signal of the 1.8V regulator (APW8805) pulls the RESET_OUT# low, provided that it has a power supply!
The 1.8V regulator is supplied from VDD_5V0_IO_SYS, and this voltage is present after a time delay from CARRIER_PWR_ON.
See t6 in the Figure 8. At this time, the Jetson module 1.8V rail is present, pulling up the RESET_OUT# pin, and the CARRIER_PWR_ON has not been yet applied, and all supply rails on the carrier board are at zero volts.
PGOOD is actively held low in shutdown in APW8805.
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