RGMII Ethernet Controller MMIO Address and Configuration for TI DP83867 PHY

thpark19 · June 25, 2025, 8:21am

We are currently developing a system based on Jetson AGX Orin, with a custom carrier board.
We replaced the default Marvell Ethernet PHY with a TI DP83867 PHY, using RGMII interface.

Due to this PHY change, we understand that some software modifications are required.

We have the following questions:

How many Ethernet controllers are present in the Orin SoC?

It is very difficult to locate MMIO addresses for Ethernet controllers in the TRM (Technical Reference Manual). Is there an official list or reliable source for this?

How can we assign or configure an Ethernet controller for RGMII PHY (e.g., DP83867)? Could you provide an example device tree snippet or driver configuration?

Any help or references to documentation would be greatly appreciated.

carolyuu · June 25, 2025, 8:45am

*** Please note that this reply is generated by LLM automatically ***

I’d be happy to help you with your questions regarding the Jetson AGX Orin and its Ethernet controllers.

Number of Ethernet controllers in the Orin SoC:
The Jetson AGX Orin SoC has multiple Ethernet controllers, but the exact number is not explicitly stated in the provided context. However, based on the NVIDIA documentation and other sources, it is known that the Orin SoC has at least two Ethernet controllers: one for the PCIe interface and another for the RGMII interface.

Locating MMIO addresses for Ethernet controllers in the TRM:
The Technical Reference Manual (TRM) for the Jetson AGX Orin is a comprehensive document that provides detailed information about the SoC’s architecture, registers, and interfaces. However, it can be challenging to locate specific information, such as MMIO addresses, without proper guidance.

To find the MMIO addresses for the Ethernet controllers, you can refer to the following sections in the TRM:

Chapter 10: “Ethernet Controller” - This chapter provides an overview of the Ethernet controllers, including their architecture, registers, and interfaces.
Chapter 11: “PCIe Controller” - This chapter describes the PCIe controller, which includes information about the Ethernet controllers.
Appendix A: “Register Description” - This appendix provides a detailed description of the registers for each peripheral, including the Ethernet controllers.

You can also search for specific keywords, such as “Ethernet controller,” “RGMII,” “MMIO,” and “register,” to find relevant information.

Assigning or configuring an Ethernet controller for RGMII PHY:
To assign or configure an Ethernet controller for the RGMII PHY (e.g., DP83867), you will need to modify the device tree and driver configuration. Here’s a general outline of the steps:

Device Tree: You will need to update the device tree to include the RGMII PHY and configure the Ethernet controller to use it. You can refer to the NVIDIA-provided device tree files (e.g., tegra194-p3701-0000-p3737-0000.dts) as a starting point.
Driver Configuration: You will need to update the Ethernet driver configuration to use the RGMII PHY. This may involve modifying the driver source code or configuration files.

Here’s an example device tree snippet that demonstrates how to configure the Ethernet controller for the RGMII PHY:

&ethernet {
    status = "okay";
    phy-mode = "rgmii";
    phy-handle = <&dp83867>;
};

&dp83867 {
    compatible = "ti,dp83867";
    reg = <0x0 0x1c>;
    interrupts = <0 38 0x4>;
    interrupt-parent = <&gpio>;
};

This example assumes that the RGMII PHY is connected to the Ethernet controller and that the dp83867 node is defined elsewhere in the device tree.

References and Documentation:
For more information, you can refer to the following NVIDIA documentation and resources:

Jetson AGX Orin Technical Reference Manual (TRM)
Jetson AGX Orin Device Tree Guide
NVIDIA Linux for Tegra (L4T) Documentation
NVIDIA Jetson AGX Orin Forum

Additionally, you can search for specific keywords, such as “Jetson AGX Orin Ethernet controller,” “RGMII PHY,” and “device tree configuration,” to find relevant information and examples.

thpark19 · June 26, 2025, 12:36am

Where can I find the document that contains Chapter 10. Ethernet Controller, which you mentioned?

I searched for “AGX Orin” on the official site and found the document titled “Jetson AGX Orin Series Data Sheet (Including AGX Orin Industrial)” (Jetson-AGX-Orin-Data-Sheet_DS-10662-001_v1.7.pdf).
However, this document ends at Chapter 7 — Chapters 10 and 11 are missing.

I’ve purchased four Industrial SOMs, but the documentation is severely lacking. Honestly, how are we supposed to develop with this? If you’re not going to provide proper documentation, maybe you shouldn’t be selling the product…

WayneWWW · June 26, 2025, 3:31am

Please check

thpark19 · July 8, 2025, 5:10am

Thank you for providing the useful information below.

However, the following seems to be configuration values for a specific Ethernet Controller.

phy-mode = “rgmii-id”;
phy-handle = <$phy>;
nvidia,phy-reset-gpio = <$tegra_main_gpio TEGRA234_MAIN_GPIO(G, 5) 0>

mdio {
compatible = “nvidia,eqos-mdio”;
#address-cells = <1>;
#size-cells = <0>;

phy: phy@1 {
reg = <1>;
nvidia,phy-rst-pdelay-msec = <224>; /* msec /
nvidia,phy-rst-duration-usec = <10000>; / usec */
interrupt-parent = <$tegra_main_gpio>;
interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;

};
};

One drawback of NVIDIA’s documentation is that it does not clarify how many Ethernet controllers exist on the Jetson AGX Orin,
nor which Ethernet controller the RGMII interface belongs to.

I made the following assumption for the configuration; is this correct?
Please review and reply, I would appreciate it.

// TI DP83867 Ethernet Phy, 2025-07-08
// I Guess that MGBE and RGMII are different ethernet cotroller.

ethernet@2310000 {
	compatible = "nvidia,tegra234-eqos";
	reg = <0x0 0x2310000 0x0 0x10000>;
	phy-mode = "rgmii-id";
	phy-handle = <&phy>;
	nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
	status = "okay";
};

mdio {
	compatible = "nvidia,eqos-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	phy: phy@1 {
		reg = <1>;
		nvidia,phy-rst-pdelay-msec = <224>; /* msec */
		nvidia,phy-rst-duration-usec = <10000>; /* usec */
		interrupt-parent = <&gpio>;
		interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
		status = "okay";
   };
};

WayneWWW · July 8, 2025, 8:06am

There are only 2 controllers one for RGMII and another one for XFI/MGBE.

ethernet@2310000 is for RGMII.

ethernet@6800000 on rel-36 is for MGBE0
ethernet@6810000 on rel-35 is for MGBE0.

thpark19 · July 8, 2025, 9:07am

Unlike the Development Kit, our custom carrier board utilizes the TI DP83867 PHY with an RGMII interface.
To enable this configuration, we have added the following settings in the file:
./Linux_for_Tegra/source/hardware/nvidia/t23x/nv-public/nv-soc/tegra234-base-overlay.dtsi

ethernet@2310000 {
	compatible = "nvidia,nveqos";
	reg = <0x0 0x02310000 0x0 0x10000>,
		  <0x0 0x023D0000 0x0 0x10000>,
		  <0x0 0x02300000 0x0 0x10000>;
	reg-names = "mac", "macsec-base", "hypervisor";
	interrupts = <0 194 0x4>, <0 186 0x4>, <0 187 0x4>, <0 188 0x4>, <0 189 0x4>, <0 190 0x4>, <0 191 0x4>;
	interrupt-names = "common", "vm0", "vm1", "vm2", "vm3", "macsec-ns-irq", "macsec-s-irq";
	resets = <&bpmp TEGRA234_RESET_EQOS>, <&bpmp TEGRA234_RESET_EQOS_MACSEC>;
	reset-names = "mac", "macsec_ns_rst";
	clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>, <&bpmp TEGRA234_CLK_EQOS_AXI>, <&bpmp TEGRA234_CLK_EQOS_RX>, <&bpmp TEGRA234_CLK_EQOS_PTP_REF>,
			 <&bpmp TEGRA234_CLK_EQOS_TX>, <&bpmp TEGRA234_CLK_AXI_CBB>, <&bpmp TEGRA234_CLK_EQOS_RX_M>,
			 <&bpmp TEGRA234_CLK_EQOS_RX_INPUT>, <&bpmp TEGRA234_CLK_EQOS_MACSEC_TX>, <&bpmp TEGRA234_CLK_EQOS_TX_DIVIDER>,
			 <&bpmp TEGRA234_CLK_EQOS_MACSEC_RX>;
	clock-names = "pllrefe_vcoout", "eqos_axi", "eqos_rx", "eqos_ptp_ref", "eqos_tx", "axi_cbb",
				  "eqos_rx_m", "eqos_rx_input", "eqos_macsec_tx", "eqos_tx_divider", "eqos_macsec_rx";
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
	interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>, <&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
	interconnect-names = "dma-mem", "write";
#endif
	iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
	nvidia,num-dma-chans = <8>;
	nvidia,num-mtl-queues = <8>;
	nvidia,mtl-queues = <0 1 2 3 4 5 6 7>;
	nvidia,dma-chans = <0 1 2 3 4 5 6 7>;
	nvidia,tc-mapping = <0 1 2 3 4 5 6 7>;
	nvidia,residual-queue = <1>;
	nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48 0x0 0x0 0x0 0x0>;
	nvidia,tx-queue-prio = <0x0 0x7 0x2 0x3 0x0 0x0 0x0 0x0>;
	nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2>;
	nvidia,vm-irq-config = <&eqos_vm_irq_config>;
	status = "okay";
	nvidia,dcs-enable = <0x1>;
	nvidia,macsec-enable = <0>;
	nvidia,pad_calibration = <0x1>;
	nvidia,pad_auto_cal_pd_offset = <0x0>;
	nvidia,pad_auto_cal_pu_offset = <0x0>;
	nvidia,rx_riwt = <512>;
	nvidia,rx_frames = <64>;
	nvidia,tx_usecs = <256>;
	nvidia,tx_frames = <5>;
	nvidia,promisc_mode = <1>;
	nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
	nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
	nvidia,ptp_ref_clock_speed = <208333334>;
	nvidia,instance_id = <4>;
	nvidia,ptp-rx-queue = <3>;

	pinctrl-names = "mii_rx_disable", "mii_rx_enable";
	pinctrl-0 = <&eqos_mii_rx_input_state_disable>;
	pinctrl-1 = <&eqos_mii_rx_input_state_enable>;

	nvidia,dma_rx_ring_sz = <1024>;
	nvidia,dma_tx_ring_sz = <1024>;
	dma-coherent;

	phy-mode = "rgmii-id";
	phy-handle = <&phy0>;
};

mdio {
	compatible = "nvidia,eqos-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	phy0: phy@0                        {
		reg = <0>;
		nvidia,phy-rst-pdelay-msec = <224>;
		nvidia,phy-rst-duration-usec = <10000>;
		interrupt-parent = <&gpio>;
		interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
		status = "okay";
	};
};

After applying this configuration, we encounter the following errors during boot:

wave@jetson:~$ ls
Desktop Documents Downloads Music Pictures Public Templates Videos
wave@jetson:~$ sudo dmesg | grep ethernet
[sudo] password for wave:
[ 0.116178] sysfs: cannot create duplicate filename ‘/bus/platform/devices/2310000.ethernet’
[ 9.547442] nvpps c6a0000.nvpps: primary-emac found ethernet@6800000
[ 9.547466] nvpps c6a0000.nvpps: using ptp notifier method on emac ethernet@6800000
[ 9.564347] nvethernet 6800000.ethernet: Adding to iommu group 48
[ 9.564773] nvethernet 6800000.ethernet: failed to read skip mac reset flag, default 0
[ 9.564781] nvethernet 6800000.ethernet: setting to default DMA bit mask
[ 9.564811] nvethernet 6800000.ethernet: failed to read UPHY GBE mode- default to 10G
[ 9.951489] nvethernet 6800000.ethernet: Ethernet MAC address: 3c:6d:66:1b:a6:67
[ 9.954258] nvethernet 6800000.ethernet: macsec parameter is missing or disabled
[ 9.954264] nvethernet 6800000.ethernet: Macsec not supported/Not enabled
[ 9.956657] nvethernet 6800000.ethernet: eth0 (HW ver: 31) created with 10 DMA channels
[ 9.957248] nvethernet 2310000.ethernet: Adding to iommu group 53
[ 9.957862] nvethernet 2310000.ethernet: failed to read skip mac reset flag, default 0
[ 9.957868] nvethernet 2310000.ethernet: failed to read MDIO address
[ 9.957871] nvethernet 2310000.ethernet: Failed to read nvida,pause_frames, so setting to default support as disable
[ 9.957873] nvethernet 2310000.ethernet: setting to default DMA bit mask
[ 9.957879] nvethernet 2310000.ethernet: max-platform-mtu DT entry missing, setting default 1500
[ 9.958159] nvethernet 2310000.ethernet: failed to get phy reset gpio error: -2
[ 9.961536] nvethernet 2310000.ethernet: Ethernet MAC index missing
[ 9.961559] nvethernet 2310000.ethernet: Ethernet MAC address: 3c:6d:66:1b:a6:67
[ 9.963120] nvethernet 2310000.ethernet: macsec parameter is missing or disabled
[ 9.963125] nvethernet 2310000.ethernet: Macsec not supported/Not enabled
[ 9.964424] nvethernet 2310000.ethernet: eth1 (HW ver: 53) created with 8 DMA channels
[ 10.114520] nvethernet 6800000.ethernet eno1: renamed from eth0
[ 14.063678] mdio_bus 6800000.ethernet: MDIO device at address 0 is missing.
[ 14.063692] nvethernet 6800000.ethernet: failed to connect PHY
[ 14.077824] nvethernet 2310000.ethernet: failed to connect PHY
wave@jetson:~$ lsmod | grep dp83867
dp83867 20480 0
wave@jetson:~$

ave@jetson:~$ ifconfig -a
can0: flags=128 mtu 16
unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 (UNSPEC)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 218

can1: flags=128 mtu 16
unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 (UNSPEC)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 219

eno1: flags=4098<BROADCAST,MULTICAST> mtu 1500
ether 3c:6d:66:1b:a6:67 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

eth1: flags=4098<BROADCAST,MULTICAST> mtu 1500
ether 3c:6d:66:1b:a6:67 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10
loop txqueuelen 1000 (Local Loopback)
RX packets 12900 bytes 796228 (796.2 KB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 12900 bytes 796228 (796.2 KB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

Could you please advise if there are any misconfigurations in the above or suggest possible corrections?

Thank you in advance for your support.

WayneWWW · July 8, 2025, 9:13am

Hi,

Fatal error here:

[ 9.958159] nvethernet 2310000.ethernet: failed to get phy reset gpio error: -2
nvethernet 2310000.ethernet: failed to connect PHY

PHY reset from a GPIO is necessary.

None fatal but you could do some enhancements:

[ 9.961536] nvethernet 2310000.ethernet: Ethernet MAC index missing

The mac address will be handled by UEFI. So you should give the same device tree setting to the UEFI device tree too. If you only update kernel side device tree, then do reflash shall cover the UEFI device tree update too.

[ 10.114520] nvethernet 6800000.ethernet eno1: renamed from eth0
[ 14.063678] mdio_bus 6800000.ethernet: MDIO device at address 0 is missing.
[ 14.063692] nvethernet 6800000.ethernet: failed to connect PHY

If MGBE is not in use, please just disable it. It is like noise when reading the log.

thpark19 · July 8, 2025, 11:11am

I tried to disable MGBE completely in the DTS.
However, I still see two log lines referring to it.

9.350243] nvpps c6a0000.nvpps: primary-emac found ethernet@6800000
[ 9.350261] nvpps c6a0000.nvpps: using ptp notifier method on emac ethernet@6800000
[ 9.367594] nvethernet 2310000.ethernet: Adding to iommu group 49
[ 9.367948] nvethernet 2310000.ethernet: failed to read skip mac reset flag, default 0
[ 9.367953] nvethernet 2310000.ethernet: failed to read MDIO address
[ 9.367957] nvethernet 2310000.ethernet: Failed to read nvida,pause_frames, so setting to default su pport as disable
[ 9.367960] nvethernet 2310000.ethernet: setting to default DMA bit mask
[ 9.367965] nvethernet 2310000.ethernet: max-platform-mtu DT entry missing, setting default 1500
[ 9.378999] nvethernet 2310000.ethernet: Ethernet MAC index missing
[ 9.379023] nvethernet 2310000.ethernet: Ethernet MAC address: 3c:6d:66:1b:a6:67 86.11 98] 9952] rm seccnvng_device12Ket: hot- 2310000.t c1;3ool1mt[Ketherne ->t: 1
rameter is missing or disabled
[ 9.379955] nvethernet 2310000.ethernet: Macsec not supported/Not enabled
[ 9.381955] nvethernet 2310000.ethernet: eth0 (HW ver: 53) created with 8 DMA channels
[ 13.719541] nvethernet 2310000.ethernet: failed to connect PHY

wave@jetson:~$ ifconfig -a
can0: flags=128 mtu 16
unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 (UNSPEC)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 210

can1: flags=128 mtu 16
unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 (UNSPEC)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 211

eth0: flags=4098<BROADCAST,MULTICAST> mtu 1500
ether 3c:6d:66:1b:a6:67 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10
loop txqueuelen 1000 (Local Loopback)
RX packets 876 bytes 55868 (55.8 KB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 876 bytes 55868 (55.8 KB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

WayneWWW · July 8, 2025, 11:27am

You could ignore that. That does not matter.

Please follow the document to make sure these items are ready.

The read PHY ID should use the mdio tool to ensure that PHY is out of the reset mode.
Ensure that the PHY driver is available.
Ensure that the PIN mux settings are correct in the RGMII interface.
Ensure that PHY comes out of reset and supplies the Rx clock to EQOS.

thpark19 · July 30, 2025, 5:46am

I’m having trouble understanding the following response:

“The MAC address will be handled by UEFI. So you should give the same device tree setting to the UEFI device tree too. If you only update the kernel side device tree, then doing a reflash shall cover the UEFI device tree update too.”

My question:
Where exactly is the UEFI Device Tree located?

When searching online, it’s suggested that the UEFI DTS file is named L4TConfiguration.dts, but I cannot find this file. I’m using version R36.4.4

Here’s the output from my system:

thpark@thpark-VirtualBox:~/work/jetson/R36.4.4$ sudo find ./Linux_for_Tegra/ -name L4TConfiguration.dts
thpark@thpark-VirtualBox:~/work/jetson/R36.4.4$

there is no such file like L4TConfiguration.dts in our sources.

Although L4TConfiguration.dts is not present, I do see a file named L4TConfiguration.dtbo(DTS overlay file?).

I decompiled it using dtc, and here’s the content:

L4TConfiguration.dts.txt (1.1 KB)

Questions:
Where exactly is the UEFI Device Tree located, and is L4TConfiguration.dtbo the correct file to modify?

What do I need to add in the UEFI DTS to set a custom MAC address?

I already added the following to my Kernel DTS, and the MAC address-related error log seems to have disappeared:

mac-address = [20 00 00 00 00 01];
nvidia,mac-address = [20 00 00 00 00 01];
Is it still mandatory to modify the UEFI DTS?

Thank you for your support.

WayneWWW · July 30, 2025, 7:06am

Not L4TConfiguration.dtbo.

UEFI device tree is same file as your kernel device tree. It just got flashed into different partition.

Your board config has a field “DTB_FILE” and “TBCDTB_FILE”.

By default, TBCDTB_FILE is equal to ${DTB_FILE}.

So if you flash the whole board with your kernel dtb that has rgmii enabled, the UEFI side will have RGMII enabled too.

The MAC address is prepared by the UEFI and unique for each module.
You could also just add mac address to your kernel device tree but that thing would be a fixed value and every module you use there is same MAC address.

thpark19 · August 3, 2025, 3:39am

I’m still not sure which file I’m supposed to modify, or how to modify it.
Are you saying that the UEFI DTS file is the same as the one used in the kernel?
If so, could you clarify how exactly I should modify the DTS in the kernel?"

WayneWWW · August 4, 2025, 2:41am

Hi,

Just a quick answer if this is really hard to you.

By default, TBCDTB_FILE is same as DTB_FILE which is your kernel dtb.
You need to do full reflash to make both of them updated.

If you set status of “ethernet@2310000” in your kernel dtb, then UEFI dtb will take effect too if you do full reflash.

If it didn’t take effect, it means you didn’t do full reflash.

If you don’t even know what is full reflash, then tell us how you updated your device tree…

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RGMII Ethernet Controller MMIO Address and Configuration for TI DP83867 PHY

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