RGMII Ethernet not working

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
1

Hello,

We are struggling to get the RGMII Ethernet running based on Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide 1 documentation for Jetpack.

The logs from sudo dmesg | grep 2310000 are

[   11.723712] nvethernet 2310000.ethernet: Adding to iommu group 54
[   11.852473] nvethernet 2310000.ethernet: failed to read skip mac reset flag, default 0
[   11.852483] nvethernet 2310000.ethernet: failed to read MDIO address
[   11.852488] nvethernet 2310000.ethernet: setting to default DMA bit mask
[   12.141366] nvethernet 2310000.ethernet: Ethernet MAC address: 3c:6d:66:18:bc:9f
[   12.205933] nvethernet 2310000.ethernet: Macsec not enabled
[   12.205937] nvethernet 2310000.ethernet: Macsec: Reduced MTU: 1466 Max: 1500
[   12.214332] nvethernet 2310000.ethernet: eth1 (HW ver: 53) created with 8 DMA channels
[   12.563479] mdio_bus 2310000.ethernet: MDIO device at address 0 is missing.
[   12.563531] nvethernet 2310000.ethernet: failed to connect PHY

fulldmesg.txt (70.6 KB)

ethtool eth1 says Link detected: no

We are on a custom carrier board with SKU 5, using L4T 36.3 and follow the Kernel customization workflow.

We fixed these things that we have considered errors:

  1. Replaced all phandles from “$” to “&” , so the device-tree-compiler does not complain
  2. Fixed typo in nvidia,phy-reset-gpio = <$tegra_main_gpio TEGRA234_MAIN_GPIO(g, $) 0> to nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>
  3. When we use &tegra_main_gpio the resulting system does not boot. We instead replaced it with &gpio based on some other forum posts which lets the board boot

Additional to the changes in the documentation:
4. We added TEGRA234_MAIN_GPIO(G, 4) and TEGRA234_MAIN_GPIO(G, 5) to the gpio config in the gpio-input section (Is that the correct one for G 5?).
5. We disabled ethernet@680000 and changed its phy address to 1 on MDIO
6. We changed the ethernet@2310000 phy address to 0 on MDIO
7. We built, added and start the dp83867 kernel module on boot to support our PHY model

Our dtbo source:

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Overlay for RGMII Gigabit Ethernet PHY
 * This overlay configures the EQOS Ethernet controller to use an external PHY
 * connected via RGMII interface.
 * Based on https://docs.nvidia.com/jetson/archives/r36.4/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#for-rgmii
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
	overlay-name = "RGMII Gigabit Ethernet PHY";

	compatible = "nvidia,tegra234";

	fragment@0 {
		target-path = "/bus@0/ethernet@2310000";
		__overlay__ {
			status = "okay";
			nvidia,mac-addr-idx = <0>;
			nvidia,max-platform-mtu = <1500>;
			nvidia,pause_frames = <0>;
			local-mac-adress = [1a 2b 3c 4d 5e 6f];
			phy-mode = "rgmii-id";
			phy-handle = <&phy>;
			nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;

			mdio {
				compatible = "nvidia,eqos-mdio";
				#address-cells = <1>;
				#size-cells = <0>;

				phy: phy@0 {
					reg = <0>;
					nvidia,phy-rst-pdelay-msec = <224>; /* msec */
					nvidia,phy-rst-duration-usec = <10000>; /* usec */
					interrupt-parent = <&gpio>;
					interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
					// Extra settings based on https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ti%2Cdp83867.yaml
					compatible = "ti,dp83867", "ethernet-phy-ieee802.3-c45";
					tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
					rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
					ti,max-output-impedance;
					ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
				};
			};
		};
	};
};

The gpio config

/*This dtsi file was generated by anyboard01.xlsm Revision: 2.01 */
/*
 * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: BSD-3-Clause
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 * 
 * 3. Neither the name of the copyright holder nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS'
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "tegra234-gpio.h"


/ {
	gpio@2200000 {
		gpio-init-names = "default";
		gpio-init-0 = <&gpio_main_default>;

		gpio_main_default: default {
			gpio-input = <
				TEGRA234_MAIN_GPIO(B, 0)
				TEGRA234_MAIN_GPIO(Y, 3)
				TEGRA234_MAIN_GPIO(Y, 4)
				TEGRA234_MAIN_GPIO(Z, 1)
				TEGRA234_MAIN_GPIO(Z, 2)
				TEGRA234_MAIN_GPIO(Z, 3)
				TEGRA234_MAIN_GPIO(Z, 4)
				TEGRA234_MAIN_GPIO(Z, 5)
				TEGRA234_MAIN_GPIO(Z, 6)
				TEGRA234_MAIN_GPIO(Z, 7)
				TEGRA234_MAIN_GPIO(P, 4)
				TEGRA234_MAIN_GPIO(P, 6)
				TEGRA234_MAIN_GPIO(Q, 6)
				TEGRA234_MAIN_GPIO(Q, 7)
				TEGRA234_MAIN_GPIO(R, 1)
				TEGRA234_MAIN_GPIO(N, 4)
				TEGRA234_MAIN_GPIO(N, 1)
				TEGRA234_MAIN_GPIO(G, 0)
				TEGRA234_MAIN_GPIO(G, 1)
				TEGRA234_MAIN_GPIO(G, 2)
				TEGRA234_MAIN_GPIO(G, 4)
				TEGRA234_MAIN_GPIO(G, 5)
				TEGRA234_MAIN_GPIO(G, 7)
				TEGRA234_MAIN_GPIO(H, 0)
				TEGRA234_MAIN_GPIO(H, 7)
				TEGRA234_MAIN_GPIO(I, 0)
				TEGRA234_MAIN_GPIO(I, 1)
				TEGRA234_MAIN_GPIO(I, 2)
				TEGRA234_MAIN_GPIO(AC, 3)
				TEGRA234_MAIN_GPIO(AC, 4)
				TEGRA234_MAIN_GPIO(AC, 5)
				TEGRA234_MAIN_GPIO(AE, 0)
				TEGRA234_MAIN_GPIO(AE, 1)
				TEGRA234_MAIN_GPIO(K, 0)
				TEGRA234_MAIN_GPIO(K, 1)
				TEGRA234_MAIN_GPIO(K, 6)
				TEGRA234_MAIN_GPIO(K, 7)
				TEGRA234_MAIN_GPIO(L, 2)
				TEGRA234_MAIN_GPIO(L, 3)
				TEGRA234_MAIN_GPIO(AG, 2)
				TEGRA234_MAIN_GPIO(AG, 3)
				TEGRA234_MAIN_GPIO(AG, 6)
				TEGRA234_MAIN_GPIO(AG, 7)
				TEGRA234_MAIN_GPIO(AF, 2)
				TEGRA234_MAIN_GPIO(AF, 3)
				>;
			gpio-output-low = <
				TEGRA234_MAIN_GPIO(X, 0)
				TEGRA234_MAIN_GPIO(X, 1)
				TEGRA234_MAIN_GPIO(Q, 4)
				TEGRA234_MAIN_GPIO(N, 3)
				TEGRA234_MAIN_GPIO(H, 1)
				TEGRA234_MAIN_GPIO(H, 3)
				TEGRA234_MAIN_GPIO(H, 4)
				TEGRA234_MAIN_GPIO(H, 5)
				TEGRA234_MAIN_GPIO(H, 6)
				TEGRA234_MAIN_GPIO(I, 5)
				TEGRA234_MAIN_GPIO(AC, 0)
				TEGRA234_MAIN_GPIO(AC, 1)
				TEGRA234_MAIN_GPIO(AC, 2)
				TEGRA234_MAIN_GPIO(A, 1)
				TEGRA234_MAIN_GPIO(A, 2)
				>;
			gpio-output-high = <
				TEGRA234_MAIN_GPIO(Y, 0)
				TEGRA234_MAIN_GPIO(Y, 1)
				TEGRA234_MAIN_GPIO(Y, 2)
				TEGRA234_MAIN_GPIO(Z, 0)
				TEGRA234_MAIN_GPIO(Q, 1)
				TEGRA234_MAIN_GPIO(G, 3)
				TEGRA234_MAIN_GPIO(AC, 7)
				TEGRA234_MAIN_GPIO(K, 5)
				TEGRA234_MAIN_GPIO(A, 0)
				TEGRA234_MAIN_GPIO(A, 3)
				>;
		};
	};
	gpio@c2f0000 {
		gpio-init-names = "default";
		gpio-init-0 = <&gpio_aon_default>;

		gpio_aon_default: default {
			gpio-input = <
				TEGRA234_AON_GPIO(EE, 5)
				TEGRA234_AON_GPIO(EE, 6)
				TEGRA234_AON_GPIO(EE, 2)
				TEGRA234_AON_GPIO(EE, 4)
				TEGRA234_AON_GPIO(CC, 0)
				TEGRA234_AON_GPIO(CC, 1)
				TEGRA234_AON_GPIO(CC, 2)
				TEGRA234_AON_GPIO(CC, 3)
				TEGRA234_AON_GPIO(AA, 0)
				TEGRA234_AON_GPIO(AA, 1)
				TEGRA234_AON_GPIO(AA, 2)
				TEGRA234_AON_GPIO(AA, 3)
				>;
			gpio-output-low = <
				>;
			gpio-output-high = <
				TEGRA234_AON_GPIO(BB, 3)
				>;
		};
	};
	gpio@9250000 {
		gpio-init-names = "default";
		gpio-init-0 = <&gpio_fsi_default>;

		gpio_fsi_default: default {
			gpio-input = <
				>;
			gpio-output-low = <
				>;
			gpio-output-high = <
				>;
		};
	};

};

The pinmux:

/*This dtsi file was generated by anyboard01.xlsm Revision: 2.01 */
/*
 * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: BSD-3-Clause
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 * 
 * 3. Neither the name of the copyright holder nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS'
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;
#include "pinctrl-tegra.h"

#include "./Orin-anyboard01-gpio-default.dtsi"
/ {
	pinmux@2430000 {
		pinctrl-names = "default", "drive", "unused";
		pinctrl-0 = <&pinmux_default>;
		pinctrl-1 = <&drive_default>;
		pinctrl-2 = <&pinmux_unused_lowpower>;

		pinmux_default: common {
			/* SFIO Pin Configuration */
			shutdown_n {
				nvidia,pins = "shutdown_n";
				nvidia,function = "shutdown";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			batt_oc_pee3 {
				nvidia,pins = "batt_oc_pee3";
				nvidia,function = "soc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			hdmi_cec_pgg0 {
				nvidia,pins = "hdmi_cec_pgg0";
				nvidia,function = "hdmi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			touch_clk_pcc4 {
				nvidia,pins = "touch_clk_pcc4";
				nvidia,function = "gp";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart3_tx_pcc5 {
				nvidia,pins = "uart3_tx_pcc5";
				nvidia,function = "uartc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart3_rx_pcc6 {
				nvidia,pins = "uart3_rx_pcc6";
				nvidia,function = "uartc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			gen2_i2c_scl_pcc7 {
				nvidia,pins = "gen2_i2c_scl_pcc7";
				nvidia,function = "i2c2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			gen2_i2c_sda_pdd0 {
				nvidia,pins = "gen2_i2c_sda_pdd0";
				nvidia,function = "i2c2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			gen8_i2c_scl_pdd1 {
				nvidia,pins = "gen8_i2c_scl_pdd1";
				nvidia,function = "i2c8";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			gen8_i2c_sda_pdd2 {
				nvidia,pins = "gen8_i2c_sda_pdd2";
				nvidia,function = "i2c8";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			can0_stb_paa4 {
				nvidia,pins = "can0_stb_paa4";
				nvidia,function = "tsc_edge_out2";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can0_err_paa7 {
				nvidia,pins = "can0_err_paa7";
				nvidia,function = "tsc_edge_out3";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can1_stb_pbb0 {
				nvidia,pins = "can1_stb_pbb0";
				nvidia,function = "dmic3";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can1_en_pbb1 {
				nvidia,pins = "can1_en_pbb1";
				nvidia,function = "dmic3";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			soc_gpio50_pbb2 {
				nvidia,pins = "soc_gpio50_pbb2";
				nvidia,function = "tsc_edge_out0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			gp_pwm2_px2 {
				nvidia,pins = "gp_pwm2_px2";
				nvidia,function = "gp";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			gp_pwm3_px3 {
				nvidia,pins = "gp_pwm3_px3";
				nvidia,function = "gp";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart2_tx_px4 {
				nvidia,pins = "uart2_tx_px4";
				nvidia,function = "uartb";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart2_rx_px5 {
				nvidia,pins = "uart2_rx_px5";
				nvidia,function = "uartb";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart2_rts_px6 {
				nvidia,pins = "uart2_rts_px6";
				nvidia,function = "uartb";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart2_cts_px7 {
				nvidia,pins = "uart2_cts_px7";
				nvidia,function = "uartb";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart5_tx_py5 {
				nvidia,pins = "uart5_tx_py5";
				nvidia,function = "uarti";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart5_rx_py6 {
				nvidia,pins = "uart5_rx_py6";
				nvidia,function = "uarti";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			extperiph1_clk_pp0 {
				nvidia,pins = "extperiph1_clk_pp0";
				nvidia,function = "extperiph1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			extperiph2_clk_pp1 {
				nvidia,pins = "extperiph2_clk_pp1";
				nvidia,function = "extperiph2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			cam_i2c_scl_pp2 {
				nvidia,pins = "cam_i2c_scl_pp2";
				nvidia,function = "i2c3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			cam_i2c_sda_pp3 {
				nvidia,pins = "cam_i2c_sda_pp3";
				nvidia,function = "i2c3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio24_pp5 {
				nvidia,pins = "soc_gpio24_pp5";
				nvidia,function = "soc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pwr_i2c_scl_pp7 {
				nvidia,pins = "pwr_i2c_scl_pp7";
				nvidia,function = "i2c5";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pwr_i2c_sda_pq0 {
				nvidia,pins = "pwr_i2c_sda_pq0";
				nvidia,function = "i2c5";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio29_pq2 {
				nvidia,pins = "soc_gpio29_pq2";
				nvidia,function = "nv";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio32_pq5 {
				nvidia,pins = "soc_gpio32_pq5";
				nvidia,function = "extperiph3";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio37_pr0 {
				nvidia,pins = "soc_gpio37_pr0";
				nvidia,function = "gp";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart1_tx_pr2 {
				nvidia,pins = "uart1_tx_pr2";
				nvidia,function = "uarta";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart1_rx_pr3 {
				nvidia,pins = "uart1_rx_pr3";
				nvidia,function = "uarta";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart1_rts_pr4 {
				nvidia,pins = "uart1_rts_pr4";
				nvidia,function = "uarta";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart1_cts_pr5 {
				nvidia,pins = "uart1_cts_pr5";
				nvidia,function = "uarta";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch0_hpd_pm0 {
				nvidia,pins = "dp_aux_ch0_hpd_pm0";
				nvidia,function = "dp";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch1_hpd_pm1 {
				nvidia,pins = "dp_aux_ch1_hpd_pm1";
				nvidia,function = "eth3";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch2_hpd_pm2 {
				nvidia,pins = "dp_aux_ch2_hpd_pm2";
				nvidia,function = "eth3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch3_p_pn7 {
				nvidia,pins = "dp_aux_ch3_p_pn7";
				nvidia,function = "i2c9";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch3_n_pn0 {
				nvidia,pins = "dp_aux_ch3_n_pn0";
				nvidia,function = "i2c9";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch3_hpd_pm3 {
				nvidia,pins = "dp_aux_ch3_hpd_pm3";
				nvidia,function = "eth2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio55_pm4 {
				nvidia,pins = "soc_gpio55_pm4";
				nvidia,function = "eth2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio36_pm5 {
				nvidia,pins = "soc_gpio36_pm5";
				nvidia,function = "eth0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio53_pm6 {
				nvidia,pins = "soc_gpio53_pm6";
				nvidia,function = "eth0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio38_pm7 {
				nvidia,pins = "soc_gpio38_pm7";
				nvidia,function = "eth1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio40_pn2 {
				nvidia,pins = "soc_gpio40_pn2";
				nvidia,function = "eth1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio19_pg6 {
				nvidia,pins = "soc_gpio19_pg6";
				nvidia,function = "gp";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			gen1_i2c_scl_pi3 {
				nvidia,pins = "gen1_i2c_scl_pi3";
				nvidia,function = "i2c1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			gen1_i2c_sda_pi4 {
				nvidia,pins = "gen1_i2c_sda_pi4";
				nvidia,function = "i2c1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio07_pi6 {
				nvidia,pins = "soc_gpio07_pi6";
				nvidia,function = "gp";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			sdmmc1_clk_pj0 {
				nvidia,pins = "sdmmc1_clk_pj0";
				nvidia,function = "sdmmc1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_ENABLE>;
			};

			sdmmc1_cmd_pj1 {
				nvidia,pins = "sdmmc1_cmd_pj1";
				nvidia,function = "sdmmc1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			sdmmc1_dat0_pj2 {
				nvidia,pins = "sdmmc1_dat0_pj2";
				nvidia,function = "sdmmc1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			sdmmc1_dat1_pj3 {
				nvidia,pins = "sdmmc1_dat1_pj3";
				nvidia,function = "sdmmc1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			sdmmc1_dat2_pj4 {
				nvidia,pins = "sdmmc1_dat2_pj4";
				nvidia,function = "sdmmc1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			sdmmc1_dat3_pj5 {
				nvidia,pins = "sdmmc1_dat3_pj5";
				nvidia,function = "sdmmc1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			qspi0_sck_pc0 {
				nvidia,pins = "qspi0_sck_pc0";
				nvidia,function = "qspi0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_ENABLE>;
			};

			qspi0_cs_n_pc1 {
				nvidia,pins = "qspi0_cs_n_pc1";
				nvidia,function = "qspi0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			qspi0_io0_pc2 {
				nvidia,pins = "qspi0_io0_pc2";
				nvidia,function = "qspi0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			qspi0_io1_pc3 {
				nvidia,pins = "qspi0_io1_pc3";
				nvidia,function = "qspi0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			qspi0_io2_pc4 {
				nvidia,pins = "qspi0_io2_pc4";
				nvidia,function = "qspi0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			qspi0_io3_pc5 {
				nvidia,pins = "qspi0_io3_pc5";
				nvidia,function = "qspi0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			soc_gpio59_pac6 {
				nvidia,pins = "soc_gpio59_pac6";
				nvidia,function = "aud";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio45_pad0 {
				nvidia,pins = "soc_gpio45_pad0";
				nvidia,function = "i2s1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio46_pad1 {
				nvidia,pins = "soc_gpio46_pad1";
				nvidia,function = "i2s1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio47_pad2 {
				nvidia,pins = "soc_gpio47_pad2";
				nvidia,function = "i2s1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio48_pad3 {
				nvidia,pins = "soc_gpio48_pad3";
				nvidia,function = "i2s1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l1_clkreq_n_pk2 {
				nvidia,pins = "pex_l1_clkreq_n_pk2";
				nvidia,function = "pe1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l1_rst_n_pk3 {
				nvidia,pins = "pex_l1_rst_n_pk3";
				nvidia,function = "pe1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l4_clkreq_n_pl0 {
				nvidia,pins = "pex_l4_clkreq_n_pl0";
				nvidia,function = "pe4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l4_rst_n_pl1 {
				nvidia,pins = "pex_l4_rst_n_pl1";
				nvidia,function = "pe4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l7_clkreq_n_pag0 {
				nvidia,pins = "pex_l7_clkreq_n_pag0";
				nvidia,function = "pe7";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l7_rst_n_pag1 {
				nvidia,pins = "pex_l7_rst_n_pag1";
				nvidia,function = "pe7";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dap4_sclk_pa4 {
				nvidia,pins = "dap4_sclk_pa4";
				nvidia,function = "i2s4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dap4_dout_pa5 {
				nvidia,pins = "dap4_dout_pa5";
				nvidia,function = "i2s4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dap4_din_pa6 {
				nvidia,pins = "dap4_din_pa6";
				nvidia,function = "i2s4";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dap4_fs_pa7 {
				nvidia,pins = "dap4_fs_pa7";
				nvidia,function = "i2s4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l5_clkreq_n_paf0 {
				nvidia,pins = "pex_l5_clkreq_n_paf0";
				nvidia,function = "pe5";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l5_rst_n_paf1 {
				nvidia,pins = "pex_l5_rst_n_paf1";
				nvidia,function = "pe5";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			emmc_clk {
				nvidia,pins = "emmc_clk";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_ENABLE>;
			};

			emmc_cmd {
				nvidia,pins = "emmc_cmd";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dat0 {
				nvidia,pins = "emmc_dat0";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dat1 {
				nvidia,pins = "emmc_dat1";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dat2 {
				nvidia,pins = "emmc_dat2";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dat3 {
				nvidia,pins = "emmc_dat3";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dat4 {
				nvidia,pins = "emmc_dat4";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dat5 {
				nvidia,pins = "emmc_dat5";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dat6 {
				nvidia,pins = "emmc_dat6";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dat7 {
				nvidia,pins = "emmc_dat7";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,loopback = <TEGRA_PIN_DISABLE>;
			};

			emmc_dqs {
				nvidia,pins = "emmc_dqs";
				nvidia,function = "emmc";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			/* GPIO Pin Configuration */
			soc_gpio26_pee5 {
				nvidia,pins = "soc_gpio26_pee5";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio27_pee6 {
				nvidia,pins = "soc_gpio27_pee6";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			ao_retention_n_pee2 {
				nvidia,pins = "ao_retention_n_pee2";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			power_on_pee4 {
				nvidia,pins = "power_on_pee4";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi2_sck_pcc0 {
				nvidia,pins = "spi2_sck_pcc0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi2_miso_pcc1 {
				nvidia,pins = "spi2_miso_pcc1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi2_mosi_pcc2 {
				nvidia,pins = "spi2_mosi_pcc2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi2_cs0_pcc3 {
				nvidia,pins = "spi2_cs0_pcc3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			can0_dout_paa0 {
				nvidia,pins = "can0_dout_paa0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			can0_din_paa1 {
				nvidia,pins = "can0_din_paa1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			can1_dout_paa2 {
				nvidia,pins = "can1_dout_paa2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			can1_din_paa3 {
				nvidia,pins = "can1_din_paa3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			can1_err_pbb3 {
				nvidia,pins = "can1_err_pbb3";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio08_pb0 {
				nvidia,pins = "soc_gpio08_pb0";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			gpu_pwr_req_px0 {
				nvidia,pins = "gpu_pwr_req_px0";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			cv_pwr_req_px1 {
				nvidia,pins = "cv_pwr_req_px1";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi3_sck_py0 {
				nvidia,pins = "spi3_sck_py0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi3_miso_py1 {
				nvidia,pins = "spi3_miso_py1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi3_mosi_py2 {
				nvidia,pins = "spi3_mosi_py2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi3_cs0_py3 {
				nvidia,pins = "spi3_cs0_py3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi3_cs1_py4 {
				nvidia,pins = "spi3_cs1_py4";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart5_rts_py7 {
				nvidia,pins = "uart5_rts_py7";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart5_cts_pz0 {
				nvidia,pins = "uart5_cts_pz0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			usb_vbus_en0_pz1 {
				nvidia,pins = "usb_vbus_en0_pz1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			usb_vbus_en1_pz2 {
				nvidia,pins = "usb_vbus_en1_pz2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi1_sck_pz3 {
				nvidia,pins = "spi1_sck_pz3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi1_miso_pz4 {
				nvidia,pins = "spi1_miso_pz4";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi1_mosi_pz5 {
				nvidia,pins = "spi1_mosi_pz5";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi1_cs0_pz6 {
				nvidia,pins = "spi1_cs0_pz6";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi1_cs1_pz7 {
				nvidia,pins = "spi1_cs1_pz7";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio23_pp4 {
				nvidia,pins = "soc_gpio23_pp4";
				nvidia,function = "vi0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio25_pp6 {
				nvidia,pins = "soc_gpio25_pp6";
				nvidia,function = "vi0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio28_pq1 {
				nvidia,pins = "soc_gpio28_pq1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio31_pq4 {
				nvidia,pins = "soc_gpio31_pq4";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio33_pq6 {
				nvidia,pins = "soc_gpio33_pq6";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio35_pq7 {
				nvidia,pins = "soc_gpio35_pq7";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio56_pr1 {
				nvidia,pins = "soc_gpio56_pr1";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch1_p_pn3 {
				nvidia,pins = "dp_aux_ch1_p_pn3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch1_n_pn4 {
				nvidia,pins = "dp_aux_ch1_n_pn4";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio39_pn1 {
				nvidia,pins = "soc_gpio39_pn1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio13_pg0 {
				nvidia,pins = "soc_gpio13_pg0";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio14_pg1 {
				nvidia,pins = "soc_gpio14_pg1";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio15_pg2 {
				nvidia,pins = "soc_gpio15_pg2";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio16_pg3 {
				nvidia,pins = "soc_gpio16_pg3";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio20_pg7 {
				nvidia,pins = "soc_gpio20_pg7";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio21_ph0 {
				nvidia,pins = "soc_gpio21_ph0";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio22_ph1 {
				nvidia,pins = "soc_gpio22_ph1";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart4_tx_ph3 {
				nvidia,pins = "uart4_tx_ph3";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart4_rx_ph4 {
				nvidia,pins = "uart4_rx_ph4";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart4_rts_ph5 {
				nvidia,pins = "uart4_rts_ph5";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart4_cts_ph6 {
				nvidia,pins = "uart4_cts_ph6";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio41_ph7 {
				nvidia,pins = "soc_gpio41_ph7";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio42_pi0 {
				nvidia,pins = "soc_gpio42_pi0";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio43_pi1 {
				nvidia,pins = "soc_gpio43_pi1";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio44_pi2 {
				nvidia,pins = "soc_gpio44_pi2";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			cpu_pwr_req_pi5 {
				nvidia,pins = "cpu_pwr_req_pi5";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi5_sck_pac0 {
				nvidia,pins = "spi5_sck_pac0";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi5_miso_pac1 {
				nvidia,pins = "spi5_miso_pac1";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi5_mosi_pac2 {
				nvidia,pins = "spi5_mosi_pac2";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi5_cs0_pac3 {
				nvidia,pins = "spi5_cs0_pac3";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio57_pac4 {
				nvidia,pins = "soc_gpio57_pac4";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio58_pac5 {
				nvidia,pins = "soc_gpio58_pac5";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio60_pac7 {
				nvidia,pins = "soc_gpio60_pac7";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			ufs0_ref_clk_pae0 {
				nvidia,pins = "ufs0_ref_clk_pae0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			ufs0_rst_n_pae1 {
				nvidia,pins = "ufs0_rst_n_pae1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			pex_l0_clkreq_n_pk0 {
				nvidia,pins = "pex_l0_clkreq_n_pk0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l0_rst_n_pk1 {
				nvidia,pins = "pex_l0_rst_n_pk1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l2_clkreq_n_pk4 {
				nvidia,pins = "pex_l2_clkreq_n_pk4";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l2_rst_n_pk5 {
				nvidia,pins = "pex_l2_rst_n_pk5";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l3_clkreq_n_pk6 {
				nvidia,pins = "pex_l3_clkreq_n_pk6";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l3_rst_n_pk7 {
				nvidia,pins = "pex_l3_rst_n_pk7";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_wake_n_pl2 {
				nvidia,pins = "pex_wake_n_pl2";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio34_pl3 {
				nvidia,pins = "soc_gpio34_pl3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l8_clkreq_n_pag2 {
				nvidia,pins = "pex_l8_clkreq_n_pag2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l8_rst_n_pag3 {
				nvidia,pins = "pex_l8_rst_n_pag3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l9_clkreq_n_pag4 {
				nvidia,pins = "pex_l9_clkreq_n_pag4";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l9_rst_n_pag5 {
				nvidia,pins = "pex_l9_rst_n_pag5";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l10_clkreq_n_pag6 {
				nvidia,pins = "pex_l10_clkreq_n_pag6";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l10_rst_n_pag7 {
				nvidia,pins = "pex_l10_rst_n_pag7";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dap6_sclk_pa0 {
				nvidia,pins = "dap6_sclk_pa0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dap6_dout_pa1 {
				nvidia,pins = "dap6_dout_pa1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dap6_din_pa2 {
				nvidia,pins = "dap6_din_pa2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dap6_fs_pa3 {
				nvidia,pins = "dap6_fs_pa3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l6_clkreq_n_paf2 {
				nvidia,pins = "pex_l6_clkreq_n_paf2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			pex_l6_rst_n_paf3 {
				nvidia,pins = "pex_l6_rst_n_paf3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};
		};

		pinmux_unused_lowpower: unused_lowpower {
			sce_error_pee0 {
				nvidia,pins = "sce_error_pee0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			vcomp_alert_pee1 {
				nvidia,pins = "vcomp_alert_pee1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			bootv_ctl_n_pee7 {
				nvidia,pins = "bootv_ctl_n_pee7";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			can0_en_paa5 {
				nvidia,pins = "can0_en_paa5";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio49_paa6 {
				nvidia,pins = "soc_gpio49_paa6";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio30_pq3 {
				nvidia,pins = "soc_gpio30_pq3";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch2_p_pn5 {
				nvidia,pins = "dp_aux_ch2_p_pn5";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			dp_aux_ch2_n_pn6 {
				nvidia,pins = "dp_aux_ch2_n_pn6";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio17_pg4 {
				nvidia,pins = "soc_gpio17_pg4";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio18_pg5 {
				nvidia,pins = "soc_gpio18_pg5";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio06_ph2 {
				nvidia,pins = "soc_gpio06_ph2";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			qspi1_sck_pc6 {
				nvidia,pins = "qspi1_sck_pc6";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,loopback = <TEGRA_PIN_ENABLE>;
			};

			qspi1_cs_n_pc7 {
				nvidia,pins = "qspi1_cs_n_pc7";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			qspi1_io0_pd0 {
				nvidia,pins = "qspi1_io0_pd0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			qspi1_io1_pd1 {
				nvidia,pins = "qspi1_io1_pd1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			qspi1_io2_pd2 {
				nvidia,pins = "qspi1_io2_pd2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			qspi1_io3_pd3 {
				nvidia,pins = "qspi1_io3_pd3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			eqos_txc_pe0 {
				nvidia,pins = "eqos_txc_pe0";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			eqos_td0_pe1 {
				nvidia,pins = "eqos_td0_pe1";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			eqos_td1_pe2 {
				nvidia,pins = "eqos_td1_pe2";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			eqos_td2_pe3 {
				nvidia,pins = "eqos_td2_pe3";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			eqos_td3_pe4 {
				nvidia,pins = "eqos_td3_pe4";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			eqos_tx_ctl_pe5 {
				nvidia,pins = "eqos_tx_ctl_pe5";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			eqos_rd0_pe6 {
				nvidia,pins = "eqos_rd0_pe6";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			eqos_rd1_pe7 {
				nvidia,pins = "eqos_rd1_pe7";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			eqos_rd2_pf0 {
				nvidia,pins = "eqos_rd2_pf0";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			eqos_rd3_pf1 {
				nvidia,pins = "eqos_rd3_pf1";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			eqos_rx_ctl_pf2 {
				nvidia,pins = "eqos_rx_ctl_pf2";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			eqos_rxc_pf3 {
				nvidia,pins = "eqos_rxc_pf3";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			eqos_sma_mdio_pf4 {
        		nvidia,pins = "eqos_sma_mdio_pf4";
        		nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};

			eqos_sma_mdc_pf5 {
				nvidia,pins = "eqos_sma_mdc_pf5";
				nvidia,function = "eqos";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can2_dout_ps0 {
				nvidia,pins = "can2_dout_ps0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can2_din_ps1 {
				nvidia,pins = "can2_din_ps1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can2_stb_ps2 {
				nvidia,pins = "can2_stb_ps2";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can2_en_ps3 {
				nvidia,pins = "can2_en_ps3";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can2_err_ps4 {
				nvidia,pins = "can2_err_ps4";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can3_dout_ps5 {
				nvidia,pins = "can3_dout_ps5";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can3_din_ps6 {
				nvidia,pins = "can3_din_ps6";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can3_stb_ps7 {
				nvidia,pins = "can3_stb_ps7";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can3_en_pt0 {
				nvidia,pins = "can3_en_pt0";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			can3_err_pt1 {
				nvidia,pins = "can3_err_pt1";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};

			soc_error_pu0 {
				nvidia,pins = "soc_error_pu0";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart7_tx_pu1 {
				nvidia,pins = "uart7_tx_pu1";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			uart7_rx_pu2 {
				nvidia,pins = "uart7_rx_pu2";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi7_sck_pu3 {
				nvidia,pins = "spi7_sck_pu3";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi7_miso_pu4 {
				nvidia,pins = "spi7_miso_pu4";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi7_mosi_pu5 {
				nvidia,pins = "spi7_mosi_pu5";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			spi7_cs0_pu6 {
				nvidia,pins = "spi7_cs0_pu6";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio51_pu7 {
				nvidia,pins = "soc_gpio51_pu7";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio52_pv0 {
				nvidia,pins = "soc_gpio52_pv0";
				nvidia,function = "rsvd0";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio61_pw0 {
				nvidia,pins = "soc_gpio61_pw0";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};

			soc_gpio62_pw1 {
				nvidia,pins = "soc_gpio62_pw1";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
				nvidia,lpdr = <TEGRA_PIN_DISABLE>;
			};
		};

		drive_default: drive {
		};
	};
};
2 Likes
2

Checking some registers:

nvidia@tegra-ubuntu:~/mdio-tools/kernel$ sudo busybox devmem 0x02445000
0x00002400
nvidia@tegra-ubuntu:~/mdio-tools/kernel$ sudo busybox devmem 0x02434070
0x00000058
nvidia@tegra-ubuntu:~/mdio-tools/kernel$ sudo busybox devmem 0x02434078
0x00000000
1 Like
4

G5 is not a GPIO input, you should not set it.

I notice you are using a “dtbo” but not directly put it in dtb. Are you sure the thing you added really takes effect?

You could check the logic inside kernel/3rdparty/canonical/linux-jammy/kernel-source/drivers/net/mdio/of_mdio.c for that “MDIO device at address %d is missing” error.

5

By “set it”, do you mean adding it to the gpio dtsi (Change #4 that I made)? So I’ll remove both of these from the gpio config again?

It’s being added by this:
OVERLAY_DTB_FILE="${OVERLAY_DTB_FILE},tegra234-rgmii-gigabit-ethernet-phy.dtbo";

We verified on the running system that the changes are present with dtc -I fs -O dts -s -S 4 -o extracted_dt.dts /proc/device-tree

Looking at the source code (following references to drivers/net/phy/phy.c) just shows that a “no such device” rc causes this, which is returned in many different cases, most of which handle the case where ndev->phydev is nullptr.

Can you confirm that it’s okay to just replace &tegra_main_gpio (from the docs) with &gpio in the dt? Without this substitution the Jetson does not boot, but maybe that needs to be fixed in a different way.

6

As I only mentioned “G5”, you should only remove GPIO G5. Not both (if your “both” here mean G4 and G5).

Looking at the source code (following references to drivers/net/phy/phy.c ) just shows that a “no such device” rc causes this, which is returned in many different cases, most of which handle the case where ndev->phydev is nullptr.

I am not sure why you are “looking around” the code. You should put a print there, run it on your board and see which case is triggering the error on your side. Please be aware that those codes are running on your side and your machine. Only you could do the precise check.

Can you confirm that it’s okay to just replace &tegra_main_gpio (from the docs) with &gpio in the dt? Without this substitution the Jetson does not boot, but maybe that needs to be fixed in a different way.

This is actually not really important thing. You could check what is “&gpio” refer to in your device tree. It should be something like “gpio@xxxxx” and that one could just be same as tegra_main_gpio.
More important, if you put something didn’t exist there, you will get compilation error.
However, looks like you didn’t hit such thing.

7

Thanks for the support.
We removed TEGRA234_MAIN_GPIO(G, 5) from the gpio config now.

It seems to be a problem with the reset or reset timing. We now disconnected it completely from the Jetson and connected the reset pin to power over a delay RC circuit (~150ms).
With this the Ethernet works ~70% of the time.

We could also remove all DP83867 related changes in dt and kernel and some of the other changes we found in the forum, and it would still work 70% of the time.

Our dtso looks like this now:

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Overlay for RGMII Gigabit Ethernet PHY
 * This overlay configures the EQOS Ethernet controller to use an external PHY
 * connected via RGMII interface.
 * Based on https://docs.nvidia.com/jetson/archives/r36.4/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#for-rgmii
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	overlay-name = "RGMII Gigabit Ethernet PHY";

	compatible = "nvidia,tegra234";

	fragment@0 {
		target-path = "/bus@0/ethernet@2310000";
		__overlay__ {
			status = "okay";
			phy-mode = "rgmii-id";
			phy-handle = <&phy>;
			nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;

			mdio {
				compatible = "nvidia,eqos-mdio";
				#address-cells = <1>;
				#size-cells = <0>;

				phy: phy@0 {
					reg = <0>;
					nvidia,phy-rst-pdelay-msec = <224>; /* msec */
					nvidia,phy-rst-duration-usec = <10000>; /* usec */
					interrupt-parent = <&gpio>;
					interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
				};
			};
		};
	};
};

With the reset of the phy connected to the jetson however, it never works.

Could this be related to these two settings in the phy node?

nvidia,phy-rst-pdelay-msec = <224>; /* msec */
nvidia,phy-rst-duration-usec = <10000>; /* usec */

The description from the bringup guide don’t make much sense to us:
“”"

  • nvidia,phy-rst-pdelay-msec: Post delay value after bringing PHY out of reset in milliseconds.
  • nvidia,phy-rst-duration-usec: Delay between the PHY reset GPIO toggle in microseconds.
    “”"

Post delay value of what?
“Delay between” should be followed by two things.

Could you clarify this?

Could it be, that this needs to be adjusted?

8

Measuring the (disconnected) reset pin on the Jetson side leads to a pattern that looks to be correct (with periods of approx. the values mentioned above in low and up).
After that it stays high, which seems correct.

When we connect the phy to the jetson, the phy seems to pull down the reset line after this initialization pattern and then it stays low.

We’ll investigate further.

1 Like
9

我也是遇到这个问题了，我还能提供的线索是：
1 我给相同的硬件（JAO+carrier board）烧录L4T35.3.1的系统，可以成功使用eth0，烧录L4T36.4.3会报错，报错如下：

[   11.723712] nvethernet 2310000.ethernet: Adding to iommu group 54
[   11.852473] nvethernet 2310000.ethernet: failed to read skip mac reset flag, default 0
[   11.852483] nvethernet 2310000.ethernet: failed to read MDIO address
[   11.852488] nvethernet 2310000.ethernet: setting to default DMA bit mask
[   12.141366] nvethernet 2310000.ethernet: Ethernet MAC address: 3c:6d:66:18:bc:9f
[   12.205933] nvethernet 2310000.ethernet: Macsec not enabled
[   12.205937] nvethernet 2310000.ethernet: Macsec: Reduced MTU: 1466 Max: 1500
[   12.214332] nvethernet 2310000.ethernet: eth1 (HW ver: 53) created with 8 DMA channels
[   12.563479] mdio_bus 2310000.ethernet: MDIO device at address 0 is missing.
[   12.563531] nvethernet 2310000.ethernet: failed to connect PHY

我确信我改设备树的过程，对于L4T35.3.1和L4T36.4.3是一致的，只是文件发生了一些变化。

1 Like
10

Thanks for the info. This is the exact error we have. We would rather not have to go back to JP5 to test this, as it would require redoing a lot of our BSP.
@WayneWWW Have you confirmed this has worked on L4T36.4.3?

Something else we have found is a possible error in the bringup guide:
There we have
nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;, where the last 0 means “Active High”.
Our PHY expects the reset to be “Active low” though.
This may explain, why the Jetson pulls the Reset to LOW after the initialization, which keeps it in RESET:
The logic analyzer also shows the Jetson pulling down the reset (keeping it in reset) after the initialization sequence:

reset_sequence
reset_sequence6643×2128 535 KB

Changing this to
nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>; should therefore be the correct setting.

Unfortunately this does not seem to have an effect and using gpioinfo on the running system confirms this does not take effect.

still_active_low_gpio
still_active_low_gpio1358×194 38.4 KB

How do we make sure G5 stays high after the initialization? The PHY has a pull up on its side, so the Jetson is actively pulling it down…

11

Should G5 be anywhere in the gpio config? It’s not present in the default one generated from the Excel sheet nor mentioned in the bringup guide.

12

HI,

Your gpio config dtsi has the “output-high” and “output-low” option there.

If you want a default value, then you could put GPIO G5 there.

My previous comment was GPIO G5 is never an “GPIO input” so you should not put it as GPIO input in that file.

13

Do you have any idea why the reset is going low at the end then? I’ve put it into output-high in the gpio dtsi and configured it to be active-low in the dtbo.

14

What is your method to tell the reset status? Measured by multimeter? And what is your expectation for the behavior?

Are you trying to say your active-low setting in the device tree does not help?

Have you checked the status of GPIO under /sys/kernel/debug/gpio?

15

We attached a logic analyzer (see screenshot above). The sequence of high and low look correct (durations according to the values in the dtbo).

Since pulling the pin low puts it into reset, we would expect it to stay in high after finishing this sequence.

One idea we had was that maybe the bring-up guide expected the phy reset to be active high instead of low (because of the 0 in nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;). We tested both and no matter if we put 0 or 1 there, the Logic analyzer shows the same pattern on the reset.

We have checked the gpio status with gpioinfo. The result can be seen above. It’s the same if we put 0 or 1 into nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;

We don’t understand why the Jetson is pulling G5 low at the end, which keeps the phy in reset.

16

Hi,

Please use /sys/kernel/debug/gpio to check gpio status. That is the correct way.

Also, are you sure your change in device tree really take effect? I mean to avoid that situation that you think dtb is updated but turns out it is still the old one.

17

image
image822×366 75.9 KB

#include "tegra234-gpio.h"


/ {
	gpio@2200000 {
		gpio-init-names = "default";
		gpio-init-0 = <&gpio_main_default>;

		gpio_main_default: default {
			gpio-input = <
				TEGRA234_MAIN_GPIO(B, 0)
				TEGRA234_MAIN_GPIO(Y, 3)
				TEGRA234_MAIN_GPIO(Y, 4)
				TEGRA234_MAIN_GPIO(Z, 1)
				TEGRA234_MAIN_GPIO(Z, 2)
				TEGRA234_MAIN_GPIO(Z, 3)
				TEGRA234_MAIN_GPIO(Z, 4)
				TEGRA234_MAIN_GPIO(Z, 5)
				TEGRA234_MAIN_GPIO(Z, 6)
				TEGRA234_MAIN_GPIO(Z, 7)
				TEGRA234_MAIN_GPIO(P, 4)
				TEGRA234_MAIN_GPIO(P, 6)
				TEGRA234_MAIN_GPIO(Q, 6)
				TEGRA234_MAIN_GPIO(Q, 7)
				TEGRA234_MAIN_GPIO(R, 1)
				TEGRA234_MAIN_GPIO(N, 4)
				TEGRA234_MAIN_GPIO(N, 1)
				TEGRA234_MAIN_GPIO(G, 0)
				TEGRA234_MAIN_GPIO(G, 1)
				TEGRA234_MAIN_GPIO(G, 2)
				TEGRA234_MAIN_GPIO(G, 4)
				TEGRA234_MAIN_GPIO(G, 7)
				TEGRA234_MAIN_GPIO(H, 0)
				TEGRA234_MAIN_GPIO(H, 7)
				TEGRA234_MAIN_GPIO(I, 0)
				TEGRA234_MAIN_GPIO(I, 1)
				TEGRA234_MAIN_GPIO(I, 2)
				TEGRA234_MAIN_GPIO(AC, 3)
				TEGRA234_MAIN_GPIO(AC, 4)
				TEGRA234_MAIN_GPIO(AC, 5)
				TEGRA234_MAIN_GPIO(AE, 0)
				TEGRA234_MAIN_GPIO(AE, 1)
				TEGRA234_MAIN_GPIO(K, 0)
				TEGRA234_MAIN_GPIO(K, 1)
				TEGRA234_MAIN_GPIO(K, 6)
				TEGRA234_MAIN_GPIO(K, 7)
				TEGRA234_MAIN_GPIO(L, 2)
				TEGRA234_MAIN_GPIO(L, 3)
				TEGRA234_MAIN_GPIO(AG, 2)
				TEGRA234_MAIN_GPIO(AG, 3)
				TEGRA234_MAIN_GPIO(AG, 6)
				TEGRA234_MAIN_GPIO(AG, 7)
				TEGRA234_MAIN_GPIO(AF, 2)
				TEGRA234_MAIN_GPIO(AF, 3)
				>;
			gpio-output-low = <
				TEGRA234_MAIN_GPIO(X, 0)
				TEGRA234_MAIN_GPIO(X, 1)
				TEGRA234_MAIN_GPIO(Q, 4)
				TEGRA234_MAIN_GPIO(N, 3)
				TEGRA234_MAIN_GPIO(H, 1)
				TEGRA234_MAIN_GPIO(H, 3)
				TEGRA234_MAIN_GPIO(H, 4)
				TEGRA234_MAIN_GPIO(H, 5)
				TEGRA234_MAIN_GPIO(H, 6)
				TEGRA234_MAIN_GPIO(I, 5)
				TEGRA234_MAIN_GPIO(AC, 0)
				TEGRA234_MAIN_GPIO(AC, 1)
				TEGRA234_MAIN_GPIO(AC, 2)
				TEGRA234_MAIN_GPIO(A, 1)
				TEGRA234_MAIN_GPIO(A, 2)
				>;
			gpio-output-high = <
				TEGRA234_MAIN_GPIO(Y, 0)
				TEGRA234_MAIN_GPIO(Y, 1)
				TEGRA234_MAIN_GPIO(Y, 2)
				TEGRA234_MAIN_GPIO(Z, 0)
				TEGRA234_MAIN_GPIO(Q, 1)
				TEGRA234_MAIN_GPIO(G, 3)
				TEGRA234_MAIN_GPIO(G, 5)
				TEGRA234_MAIN_GPIO(AC, 7)
				TEGRA234_MAIN_GPIO(K, 5)
				TEGRA234_MAIN_GPIO(A, 0)
				TEGRA234_MAIN_GPIO(A, 3)
				>;
		};
	};
	gpio@c2f0000 {
		gpio-init-names = "default";
		gpio-init-0 = <&gpio_aon_default>;

		gpio_aon_default: default {
			gpio-input = <
				TEGRA234_AON_GPIO(EE, 5)
				TEGRA234_AON_GPIO(EE, 6)
				TEGRA234_AON_GPIO(EE, 2)
				TEGRA234_AON_GPIO(EE, 4)
				TEGRA234_AON_GPIO(CC, 0)
				TEGRA234_AON_GPIO(CC, 1)
				TEGRA234_AON_GPIO(CC, 2)
				TEGRA234_AON_GPIO(CC, 3)
				TEGRA234_AON_GPIO(AA, 0)
				TEGRA234_AON_GPIO(AA, 1)
				TEGRA234_AON_GPIO(AA, 2)
				TEGRA234_AON_GPIO(AA, 3)
				>;
			gpio-output-low = <
				>;
			gpio-output-high = <
				TEGRA234_AON_GPIO(BB, 3)
				>;
		};
	};
	gpio@9250000 {
		gpio-init-names = "default";
		gpio-init-0 = <&gpio_fsi_default>;

		gpio_fsi_default: default {
			gpio-input = <
				>;
			gpio-output-low = <
				>;
			gpio-output-high = <
				>;
		};
	};

};

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	overlay-name = "RGMII Gigabit Ethernet PHY";

	compatible = "nvidia,tegra234";

	fragment@0 {
		target-path = "/bus@0/ethernet@2310000";
		__overlay__ {
			status = "okay";
			phy-mode = "rgmii-id";
			phy-handle = <&phy>;
			nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;

			mdio {
				compatible = "nvidia,eqos-mdio";
				#address-cells = <1>;
				#size-cells = <0>;

				phy: phy@0 {
					reg = <0>;
					nvidia,phy-rst-pdelay-msec = <224>; /* msec */
					nvidia,phy-rst-duration-usec = <10000>; /* usec */
					interrupt-parent = <&gpio>;
					interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
				};
			};
		};
	};
};
18

Hi,

Please go to /proc/device-tree on your system and check. You don’t need to attach your device tree. That thing does not represent whether it is running on the board.

/proc/device-tree is the one that the system is using now.

19

We know, we checked. It’s the one we applied.

image
image652×104 15.4 KB

20

So what is the gpio behavior before you changed the gpio active high/low ?

I also notice you mentioned “remove all DP83867 related changes in dt and kernel and some of the other changes we found in the forum, and it would still work 70% of the time.”

So is the rest pin working as your expectation in this situation?

21

It never worked with the reset sequence handled by the Jetson. It worked only when we connected the reset pin to power phy-power over an RC circuit that delays the signal a few hundred ms.

With this “hacked” reset it works