Inkling Build
-I haven’t seen this anywhere else yet so I’ll start a thread. Took a little bit but we now have this running on a cluster of 8 sparks. This was designed for the B300 etc.. but it looks like there was some thought of it running on sm12x in the notes (the kernel comments name DGX Spark explicitly). Issues we found so far, will update as we go:
- scipy missing — new vLLM-main dependency, not in older CUDA-13 base images. FIX pip install scipy.
- Inkling’s Lamport collectives require MNNVL (NVLink fabric) — hard error on RoCE clusters. FIX TML shipped the escape hatch: LAMPORT_RS_SCONV=0
- tml_fa4’s Sm120 path has no paged-KV support yet — vLLM’s paged cache can’t feed it. We patch fa4_rel_attention to gather paged KV → contiguous per call , TEMP FIX
- Don’t route sm12x to the sheared/tml_fa4 rel-bias path — the Sm120 kernel there discards the relative-position bias (no bias parameter in the Sm80-inherited call). You’d get plausible-but-wrong outputs on every layer. FIX The score-mod vllm_flash_attn/cute path is the intended sm12x route.
- Two one-line bugs in the (never-before-compiled) cute Sm80/Sm120 base: flash_fwd.py references mDynamicCausal which isn’t a kernel parameter (→ NameError during DSL tracing; safe fix psc = None, dynamic_causal is SM90-only anyway), and self.is_split_kv is referenced but never assigned (→ = False in init).
- Phantom varlen work tiles → cudaErrorIllegalAddress. The SingleTileVarlenScheduler launches an upper-bound grid; Sm90 kernels check work_tile.is_valid_tile, the Sm80/Sm120 base doesn’t, so phantom tiles read cu_seqlens[num_batch+1] out of bounds. Verified with compute-sanitizer (invalid read decoded exactly to the first phantom block). One-line fix: remap phantom tiles to a real tile (duplicate compute is benign, is_valid stays false so Sm90+ unaffected).
- Warmup tracing: vLLM’s V2 model runner traces attention under FakeTensorMode — any .item() in your patch path needs a fake-tensor early-return.
- One remaining timing-dependent race, still unlocated: the cluster faults under deep async pipelines but runs clean when CUDA_ENABLE_COREDUMP_ON_EXCEPTION=1 (+ coredump flags) perturbs driver timing. We ship with the instrumentation on as a stabilizer (small overhead) until it’s found. The vLLM CUDA debugging blog ( CUDA Core Dump: An Effective Tool to Debug Memory Access Issues and Beyond | vLLM Blog ) workflow is what got us this far.
Lots of help from Claude/M3 etc… we are funnign though MTP1 draft acceptance is 60%