SATA Controller Enable with Xavier


I would like to enable internal SATA controller of Xavier.

I set status to okay in ahci-sata@3507000 and disabled ufshci@2450000.

But i didn’t see SATA controller been enable in PCI device list, is there anything step need to do?


I am not sure about your configuration. Are you using our devkit or your own custom carrier?

I was based devkit’s DTB file to modifiy config to fit our design.

Suppose AHCI controller should appear in device list.

If we would like to enable SATA controller, how to enable it?

So you removed the eSATA->PCIe? Could you elaborate your design?

Yes, we are plan to use the internal SATA controller for our carrier board.

TRM document mentioned that the SATA controller utilizes lane 10 of the x12 UPHY in Xavier, sharing the UPHY lane with UFS.

Our carrier board would like to configure the lane 10 of UPHY as SATA port.

Here is our draft design modify, please help to check:

Lane 2 - 3 : C0 (PCIe x2)
Lane 4 : USB 3.1
Lane 5 : C2 (PCIe x1)
Lane 8-9 : C4 (PCIe x2)
Lane 10 : SATA

Your design requires to change uphy lane mapping.

However, we cannot help forum user with different lane mapping from our devkit on Xavier. Please contact nvidia sales to highlight if you really need such design. Thanks.

Which document can find the uphy lane mapping?

Has the native SATA controller of Xavier been validated?

I checked the pinmux document, lane 10 was only two of function with UFS and PEX2, the SATA signal doesn’t appear in the document.

The document for uphy lane mapping would be released in next BSP. However, we won’t cover this part too much. If anyone needs help for this part, they need to contact Nvidia sales and we will decide to help or not.

As for the native SATA controller, I believe we didn’t verify it on rel-31.1 because we use PCIe interface for SATA device on devkit.

Hi Wayne,

We able to add the native SATA controller as below but storage was still not recognized.

Should the pin function be switch to SATA controller?

[ 0.889760] DTS File Name: /dvs/git/dirty/git-master_linux/kernel/kernel-4.9/arch/arm64/boot/dts/…/…/…/…/…/…/hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0001-p2822-0000-common.dtsi
[ 0.889944] DTB Build time: Mar 13 2019 00:34:33
[ 0.893908] Tegra reboot handler registered.
[ 0.895006] iommu: Adding device 3507000.ahci-sata to group 0
[ 0.903588] iommu: Adding device 14180000.pcie to group 1
[ 0.904489] iommu: Adding device 14100000.pcie to group 2

[ 4.190300] hisi_sas: driver version v1.6
[ 4.191505] tegra-ahci 3507000.ahci-sata: Missing devslp-active state
[ 4.193483] tegra-ahci 3507000.ahci-sata: AHCI 0001.0301 32 slots 2 ports 3 Gbps 0x1 impl platform mode
[ 4.193501] tegra-ahci 3507000.ahci-sata: flags: 64bit ncq sntf pm led pmp pio slum part deso sadm apst
[ 4.195014] scsi host0: tegra_ahci
[ 4.195929] scsi host1: tegra_ahci
[ 4.196172] ata1: SATA max UDMA/133 mmio [mem 0x03507000-0x03508fff] port 0x100 irq 12
[ 4.196176] ata2: DUMMY
[ 4.199929] libphy: Fixed MDIO Bus: probed
[ 4.200640] tun: Universal TUN/TAP device driver, 1.6


My answer is still same. We cannot help your usecase on forum.