We design a carrier for Nano.
The only one PCIE port of Nano can be switched between M.2 E key and M key.
Below figure is the topology.
One problem we faced, if we plug an SSD on M key, E key is empty and MUX is set on the path 1 to A. It’s supposed nothing to be detected. However, after booting to OS, SSD can be found and the link width is x2.
We did some experiments, please check below table.
Here are the questions.
- The PCIE device scan mechanism of Nano?
- By the table-Case 3, 4, 5, it seems that there’s reversal lane scan?
- If we want to avoid the problem in the previous paragraph we mentioned and hardware won’t be changed, how can software do?
Tegra PCIe supports lane reversal and the observations recorded in the table are as per the expectation.
BTW, I’m sorry I didn’t understand what is the issue here that we are trying to resolve?
Thanks for reply.
The behavior we want is if the path is set as 1 to A and no device plugged in E key connector, SSD plugged in key M won’t be detected. Is it possible to achieve this one by SW changed(Modify kernel or something to disable reversal scan or others…)?
Thanks a lot.
I’m afraid it doesn’t seem to be possible.
Is this confirmed or NVIDIA will try to find the way to modify it?
This is confirmed and there is no effort to find a way as this is the HW design.
Thanks for confirmation.
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