I have C++ code using spidev0.0 at 10Mhz and SPI mode 3.
I notice that whenever the SPI transaction is a different length than the previous transaction the Chip Select is going active (low in this case) before the clock goes idle (high). SPI requires the clock to be idle before setting CS active, otherwise the clock going idle is seen as the first clocking edge. If I change my code to always use the same transaction length the issue is not present (but my performance is much worse).
It only let me post one image at a time, here is the close-up:
Have a try below patch.
Thank you for the reply. I ended up putting an inverter on SCK so I could switch to SPI mode 1 (inverted mode 1 is mode 3). That works fine as the SPI driver is holding the clock low between transactions.
Do you know when this patch will be added to the release?
The change still review you can add it manually for current release.