I have C++ code using spidev0.0 at 10Mhz and SPI mode 3. I notice that whenever the SPI transaction is a different length than the previous transaction the Chip Select is going active (low in this case) before the clock goes idle (high). SPI requires the clock to be idle before setting CS active, o…

Have a try below patch. spi: tegra: handle cs_change in modes sw_based_cs & cs_gpios committed 03:08AM - 23 Sep 20 UTC (UTC) [turmary] turmary +14 …

SCK goes idle after CS in SPI mode 3 when changing transaction lengths

ShaneCCC December 14, 2020, 5:59am 4

Have a try below patch.