Hi All,
Our HDMI output a resolution of 3840x1080. And we find a screen distortion issue.
There is very slight horizontal scanning / lines faintly moving up the screen.
The timing values of HDMI are following.
Pixel clock: 276000000 HZ
H active: 3840
V active: 1080
H front porch: 88
V front porch: 4
H sync width: 44
V sync width: 5
H back porch: 148
V back porch: 36
Is there any way to fix this?
Thanks.
FrankPCP,
Could you share a video or photo with us? Also, does your company have tx1 or tx2? Could you also try if this issue only happens to tk1?
Hi WayneWWW,
Please download the video in link below.
[url]https://drive.google.com/file/d/1tFcAZcqF3wGysT8TdbKBpR7PNN-1a-QO/view?usp=sharing[/url]
FrankPCP,
Could you check if this happen to all the tk1 module you have or just one?
Help to answer :
Yes. This issue be shown on all TK1 board.
Regards,
Tonie
Tonie,
If the mode is 1080p or any other common mode, would there be a distortion?
Do you run this test with all clock to maximum?
Tonie,
In fact, it is hardly to see where is the distortion in your video… Could you point out where is the distortion?
Hi, WayneWWW,
As FrankPCP said, we need to have 3840 X 1080 @ 60.
And the distortion acts like a wave and start from bottom to up on screen.
We had tested 1080p and everything is good but failed in output 3840 X 1080 @ 60Hz.
We use a HDMI signal analyzer and see the real output is 3840 X 1080 @ 59.64.
I don’t know why we cannot have exactly 60Hz.
Do you have any suggestion for this ?
Hi, WayneWWW,
One more thing, as FrankPCP said, the real output of pclk is 276000000 HZ.
But, if we calculate those timing value, the pclk should be 278100000 Hz.
Tonie,
Do you mean the correct pclk from your monitor is 278100000 Hz but tk1 can only output 276000000 HZ?
yes.
And we found that the monitor we tested looks like :
if we cannot provide correct pixel clock, it shows distortion.
Tonie,
Could you provide the display edid to us?
Hi, WayneWWW,
Those data on #1 is parsed by EDID except pclk.
You can check it first.
Later I will post EDID once I have it.
Hi, WayneWWW,
Here you are :
edid:
edid[000] = 00 ff ff ff ff ff ff 00 04 72 89 02 bd b6 30 23
edid[010] = 21 16 01 03 80 35 1e 78 ca bb 04 a1 59 55 9e 28
edid[020] = 0d 50 54 00 00 00 00 00 00 00 00 00 00 00 00 00
edid[030] = 00 00 00 00 00 00 a2 6c 00 18 f1 38 2d 40 58 2c
edid[040] = 45 00 bf ae 42 00 00 1e 00 00 00 00 00 00 00 00
edid[050] = 00 00 00 00 00 00 00 00 00 00 00 00 00 fc 00 42
edid[060] = 33 36 34 5f 56 31 31 2e 30 00 00 00 00 00 00 00
edid[070] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c8
Tonie,
Could you try to hack the value return from “tegra12x_hdmi_determine_parent” and see if it is possible to get closer to your nominal pclk?
Hi, WayneWWW,
The ideal pclk is 278100000 but after this function, the calculated pclk is 276000000.
Please try to hack the return value from this function to something like 278100000*2 and see if this can work. Also, please try to modify the “ref” value in that function.
Hi, WayneWWW,
We had tried to modify that but it doesn’t work.
No matter how we modify those value in order to close 278100000, the real pclk from HDMI signal analyzer is 276000000 or 279000000.
Both 276MHz and 279MHz can see distortion issue.
Hi, WayneWWW,
I would like to know if we can change ‘ref’ ?
It’s reference clock to parent.
Is it related to hardware clock generator ?
Please comment it.
Hi, WayneWWW,
One more thing…
276000000 is the hacked value from that function…