SDMMC3: Data end bit error/CRC error in L4T 35.1

I’m working on XavierNX based custom board.

I just updated from L4T 32.7.2 to 35.1. The following error occurs during microSD card recognition.

[  555.275099] mmc1: host does not support reading read-only switch, assuming write-enable
[  555.414453] mmc1: Tuning failed, falling back to fixed sampling clock
[  555.414483] mmc1: new ultra high speed SDR104 SDHC card at address 1234
[  555.415161] mmcblk1: mmc1:1234 SA32G 29.1 GiB
[  555.416270] mmc1: Data end bit error
[  555.416396] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
[  555.416554] mmc1: sdhci: Sys addr:  0x00000008 | Version:  0x00000505
[  555.416706] mmc1: sdhci: Blk size:  0x00007200 | Blk cnt:  0x00000007
[  555.416877] mmc1: sdhci: Argument:  0x00000000 | Trn mode: 0x0000003b
[  555.417027] mmc1: sdhci: Present:   0x010b0000 | Host ctl: 0x0000001b
[  555.417172] mmc1: sdhci: Power:     0x00000001 | Blk gap:  0x00000000
[  555.417312] mmc1: sdhci: Wake-up:   0x00000000 | Clock:    0x00000007
[  555.417481] mmc1: sdhci: Timeout:   0x0000000e | Int stat: 0x00000000
[  555.417625] mmc1: sdhci: Int enab:  0x03ff000b | Sig enab: 0x03fc000b
[  555.417768] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
[  555.417932] mmc1: sdhci: Caps:      0x3f6cd08c | Caps_1:   0x18002f70
[  555.418073] mmc1: sdhci: Cmd:       0x0000123a | Max curr: 0x00000000
[  555.418215] mmc1: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0x04800e92
[  555.418616] mmc1: sdhci: Resp[2]:   0x2fcb8000 | Resp[3]:  0x00000240
[  555.419262] mmc1: sdhci: Host ctl2: 0x0000000b
[  555.423898] mmc1: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x0000007ffffff20c
[  555.430914] mmc1: sdhci: ============================================
[  555.572397] mmc1: Tuning failed, falling back to fixed sampling clock
[  555.572652] mmc1: Data end bit error

Sometimes, following CRC errors also appear.

[  215.111638] mmc1: host does not support reading read-only switch, assuming write-enable
[  215.253761] mmc1: Data CRC error

DTB is defined as below.

[tegra194-p3668-common.dtsi]

	sdhci_sd: sdhci@3440000 {
		mmc-ocr-mask = <0x0>;
		cd-inverted;
		cd-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Q, 2) 0>;
		nvidia,cd-wakeup-capable;
		mmc-ocr-mask = <0>;
		vmmc-supply = <&p3668_vdd_sdmmc1_sw>;
		status = "okay";
	};

We have already tried to change the uhs-mask.

[drivers/mmc/host/sdhci-tegra.c]
/* uhs mask can be used to mask any of the UHS modes support */
#define MMC_UHS_MASK_SDR12	0x1
#define MMC_UHS_MASK_SDR25	0x2
#define MMC_UHS_MASK_SDR50	0x4
#define MMC_UHS_MASK_DDR50	0x8
#define MMC_UHS_MASK_SDR104	0x10
#define MMC_MASK_HS200		0x20
#define MMC_MASK_HS400		0x40
#define MMC_MASK_SD_HS		0x80

With uhs-mask = 0x7F, the connection was possible with SDHC.

[  136.205897] mmc1: new high speed SDHC card at address 1234
[  136.206618] mmcblk1: mmc1:1234 SA32G 29.1 GiB
[  136.212895]  mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19

With uhs-mask = 0x10, the connection was possible with SDR50.

[   58.195569] mmc1: new ultra high speed SDR50 SDHC card at address 1234
[   58.197916] mmcblk1: mmc1:1234 SA32G 29.1 GiB
[   58.202637]  mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19

At the moment, it seems that an error occurs when connecting with SDR104.
Under L4T32.7.2 (kernel 4.9.253) environment, we could recognize same SDcard as SDR104 without any problem.
Therefore, we believe that HW is not the problem, but SW.

Could you tell me how to adjust the connection with SDR104 in L4T35.1?

what is your regulator info of “p3668_vdd_sdmmc1_sw”?

Hi, WayneWWW.

[hardware/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-fixed-regulator-p3668.dtsi]

  p3668_vdd_sdmmc1_sw: regulator@106 {
  	compatible = "regulator-fixed";
  	reg = <106>;
  	regulator-name = "vdd-sdmmc1-sw";
  	regulator-min-microvolt = <3300000>;
  	regulator-max-microvolt = <3300000>;
  	gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(T, 4) 0>;
  	enable-active-low;
  };

In our production board, T.4 is assigned as SD_PWR_EN pin.

Could you attach the full error log?

Also, is there any CRC error on your board with rel-32 release?

Could you attach the full error log?

20221129_mmc1_error_L4T35.1_full_dmesg.txt (81.1 KB)

Also, is there any CRC error on your board with rel-32 release?

No, I have never seen such error.

Hi,

Please follow below instructions and share necessary info.

  1. Please add below patch and see if issue is still.
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index a5c80a6..9352e99 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -2637,6 +2637,7 @@
 		  SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 		   SDHCI_QUIRK2_HOST_OFF_CARD_ON |
+		   SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER |
 		   SDHCI_QUIRK2_SEL_SDR104_UHS_MODE_IN_SDR50,
 	.ops  = &tegra_sdhci_ops,
 };
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a90fad4..df4d419 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3,6 +3,7 @@
  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
  *
  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
+ *  Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Thanks to the following companies for their support:
  *
@@ -3152,9 +3153,14 @@
 		 * Spec says we should do both at the same time, but Ricoh
 		 * controllers do not like that.
 		 */
-		sdhci_do_reset(host, SDHCI_RESET_CMD);
-		sdhci_do_reset(host, SDHCI_RESET_DATA);
-
+		if (host->quirks2 &
+			SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
+			sdhci_do_reset(host, SDHCI_RESET_CMD |
+					SDHCI_RESET_DATA);
+		} else {
+			sdhci_do_reset(host, SDHCI_RESET_CMD);
+			sdhci_do_reset(host, SDHCI_RESET_DATA);
+		}
 		host->pending_reset = false;
 	}



  1. If issue is still there, please also add this debug patch to driver and share new dmesg.
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 91e987a..1c02be9 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -390,7 +390,7 @@
 	u32 trim_delay;
 	u8 i;
 
-	pr_debug("======= %s: Tuning windows =======\n",
+	pr_info("======= %s: Tuning windows =======\n",
 		mmc_hostname(host->mmc));
 	reg = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
 	for (i = 0; i <= SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; i++) {
@@ -399,7 +399,7 @@
 		sdhci_writel(host, reg, SDHCI_VNDR_TUN_CTRL0_0);
 		tuning_status = sdhci_readl(host,
 					SDHCI_TEGRA_VNDR_TUNING_STATUS0);
-		pr_debug("%s: tuning window[%d]: %#x\n",
+		pr_info("%s: tuning window[%d]: %#x\n",
 			mmc_hostname(host->mmc), i, tuning_status);
 	}
 	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
@@ -407,33 +407,33 @@
 	tap_delay >>= SDHCI_CLOCK_CTRL_TAP_SHIFT;
 	trim_delay = reg & SDHCI_CLOCK_CTRL_TRIM_MASK;
 	trim_delay >>= SDHCI_CLOCK_CTRL_TRIM_SHIFT;
-	pr_debug("sdhci: Tap value: %u | Trim value: %u\n", tap_delay,
+	pr_info("sdhci: Tap value: %u | Trim value: %u\n", tap_delay,
 			trim_delay);
-	pr_debug("==================================\n");
+	pr_info("==================================\n");
 
-	pr_debug("Vendor clock ctrl: %#x\n",
+	pr_info("Vendor clock ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL));
-	pr_debug("Vendor SysSW ctrl: %#x\n",
+	pr_info("Vendor SysSW ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL));
-	pr_debug("Vendor Err interrupt status : %#x\n",
+	pr_info("Vendor Err interrupt status : %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_ERR_INTR_STATUS));
-	pr_debug("Vendor Cap overrides: %#x\n",
+	pr_info("Vendor Cap overrides: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES));
-	pr_debug("Vendor Misc ctrl: %#x\n",
+	pr_info("Vendor Misc ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL));
-	pr_debug("Vendor Misc ctrl_1: %#x\n",
+	pr_info("Vendor Misc ctrl_1: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL_1));
-	pr_debug("Vendor Misc ctrl_2: %#x\n",
+	pr_info("Vendor Misc ctrl_2: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL_2));
-	pr_debug("Vendor IO trim ctrl: %#x\n",
+	pr_info("Vendor IO trim ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_IO_TRIM_CTRL_0));
-	pr_debug("Vendor Tuning ctrl: %#x\n",
+	pr_info("Vendor Tuning ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0));
-	pr_debug("SDMEM comp padctrl: %#x\n",
+	pr_info("SDMEM comp padctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL));
-	pr_debug("Autocal config: %#x\n",
+	pr_info("Autocal config: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG));
-	pr_debug("Autocal status: %#x\n",
+	pr_info("Autocal status: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_STATUS));
 }
 
@@ -771,7 +771,7 @@
 	tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
 	tegra_host->tuning_status = TUNING_STATUS_DONE;
 
-	pr_debug("%s: hw tuning done ...\n", mmc_hostname(host->mmc));
+	pr_info("%s: hw tuning done ...\n", mmc_hostname(host->mmc));
 	tegra_sdhci_dump_vendor_regs(host);
 }
  1. Also, we need you to add similar patch to your rel-32 version software and dump the same register so that we can compare the registers. Below patch is for rel-32.
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index f2e6ed3..261220e 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -403,7 +403,7 @@
 	u32 trim_delay;
 	u8 i;
 
-	pr_debug("======= %s: Tuning windows =======\n",
+	pr_err("======= %s: Tuning windows =======\n",
 				mmc_hostname(host->mmc));
 	reg = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
 	for (i = 0; i <= TUNING_WORD_SEL_MASK; i++) {
@@ -411,7 +411,7 @@
 		reg |= i;
 		sdhci_writel(host, reg, SDHCI_VNDR_TUN_CTRL0_0);
 		tuning_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUNING_STATUS0);
-		pr_debug("%s: tuning window[%d]: %#x\n",
+		pr_err("%s: tuning window[%d]: %#x\n",
 			mmc_hostname(host->mmc), i, tuning_status);
 	}
 	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
@@ -419,35 +419,35 @@
 	tap_delay &= SDHCI_CLOCK_CTRL_TAP_MASK;
 	trim_delay = reg >> SDHCI_CLOCK_CTRL_TRIM_SHIFT;
 	trim_delay &= SDHCI_CLOCK_CTRL_TRIM_MASK;
-	pr_debug("sdhci: Tap value: %u | Trim value: %u\n", tap_delay,
+	pr_err("sdhci: Tap value: %u | Trim value: %u\n", tap_delay,
 			trim_delay);
-	pr_debug("==================================\n");
+	pr_err("==================================\n");
 
-	pr_debug("Vendor clock ctrl: %#x\n",
+	pr_err("Vendor clock ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL));
-	pr_debug("Vendor SysSW ctrl: %#x\n",
+	pr_err("Vendor SysSW ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL));
-	pr_debug("Vendor Err interrupt status : %#x\n",
+	pr_err("Vendor Err interrupt status : %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_ERR_INTR_STATUS));
-	pr_debug("Vendor Cap overrides: %#x\n",
+	pr_err("Vendor Cap overrides: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES));
-	pr_debug("Vendor Misc ctrl: %#x\n",
+	pr_err("Vendor Misc ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL));
-	pr_debug("Vendor Misc ctrl_1: %#x\n",
+	pr_err("Vendor Misc ctrl_1: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL_1));
-	pr_debug("Vendor Misc ctrl_2: %#x\n",
+	pr_err("Vendor Misc ctrl_2: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL_2));
-	pr_debug("Vendor IO trim ctrl: %#x\n",
+	pr_err("Vendor IO trim ctrl: %#x\n",
 		sdhci_readl(host, SDMMC_VNDR_IO_TRIM_CTRL_0));
-	pr_debug("Vendor Tuning ctrl: %#x\n",
+	pr_err("Vendor Tuning ctrl: %#x\n",
 		sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0));
-	pr_debug("SDMEM comp padctrl: %#x\n",
+	pr_err("SDMEM comp padctrl: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL));
-	pr_debug("Autocal config: %#x\n",
+	pr_err("Autocal config: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG));
-	pr_debug("Autocal status: %#x\n",
+	pr_err("Autocal status: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_STATUS));
-	pr_debug("Tuning Status1: %#x\n",
+	pr_err("Tuning Status1: %#x\n",
 		sdhci_readl(host, SDHCI_TEGRA_VNDR_TUNING_STATUS1));
 }
 
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index e355775..0c3bfed 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2772,6 +2772,7 @@
 		else {
 			pr_err("%s: CMD CRC or end bit error, int mask %#x\n",
 				mmc_hostname(host->mmc), (unsigned)intmask);
+				sdhci_dumpregs(host);
 			host->cmd->error = -EILSEQ;
 		}
 
  1. Please add below patch and see if issue is still.

I applied the patch, but it did not resolve the issue.

[  110.736670] mmc1: host does not support reading read-only switch, assuming write-enable
[  110.885740] mmc1: Data CRC error
[  110.885851] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
[  110.886028] mmc1: sdhci: Sys addr:  0x00000008 | Version:  0x00000505
[  110.886182] mmc1: sdhci: Blk size:  0x00007200 | Blk cnt:  0x00000007
[  110.886353] mmc1: sdhci: Argument:  0x00000000 | Trn mode: 0x0000003b
[  110.886497] mmc1: sdhci: Present:   0x010b0000 | Host ctl: 0x0000001b
[  110.886642] mmc1: sdhci: Power:     0x00000001 | Blk gap:  0x00000000
[  110.886787] mmc1: sdhci: Wake-up:   0x00000000 | Clock:    0x00000007
[  110.886930] mmc1: sdhci: Timeout:   0x0000000e | Int stat: 0x00000000
[  110.887073] mmc1: sdhci: Int enab:  0x03ff000b | Sig enab: 0x03fc000b
[  110.887221] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
[  110.887370] mmc1: sdhci: Caps:      0x3f6cd08c | Caps_1:   0x18002f70
[  110.887520] mmc1: sdhci: Cmd:       0x0000123a | Max curr: 0x00000000
[  110.887668] mmc1: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0x04800e92
[  110.888063] mmc1: sdhci: Resp[2]:   0x2fcb8000 | Resp[3]:  0x00000240
[  110.888510] mmc1: sdhci: Host ctl2: 0x0000000b
[  110.893019] mmc1: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x0000007ffffff20c
[  110.900039] mmc1: sdhci: ============================================
[  111.041498] mmc1: Data CRC error
  1. If issue is still there, please also add this debug patch to driver and share new dmesg.

This is L4T35.1 dmesg.

[   70.736093] mmc1: host does not support reading read-only switch, assuming write-enable
[   70.876016] mmc1: Tuning failed, falling back to fixed sampling clock
[   70.876047] mmc1: new ultra high speed SDR104 SDHC card at address 1234
[   70.878536] mmcblk1: mmc1:1234 SA32G 29.1 GiB
[   70.879389] mmc1: Data CRC error
[   70.879504] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
[   70.879638] mmc1: sdhci: Sys addr:  0x00000008 | Version:  0x00000505
[   70.879770] mmc1: sdhci: Blk size:  0x00007200 | Blk cnt:  0x00000007
[   70.879924] mmc1: sdhci: Argument:  0x00000000 | Trn mode: 0x0000003b
[   70.880050] mmc1: sdhci: Present:   0x010b0000 | Host ctl: 0x0000001b
[   70.880176] mmc1: sdhci: Power:     0x00000001 | Blk gap:  0x00000000
[   70.880305] mmc1: sdhci: Wake-up:   0x00000000 | Clock:    0x00000007
[   70.880439] mmc1: sdhci: Timeout:   0x0000000e | Int stat: 0x00000000
[   70.880597] mmc1: sdhci: Int enab:  0x03ff000b | Sig enab: 0x03fc000b
[   70.880722] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
[   70.880849] mmc1: sdhci: Caps:      0x3f6cd08c | Caps_1:   0x18002f70
[   70.880980] mmc1: sdhci: Cmd:       0x0000123a | Max curr: 0x00000000
[   70.881272] mmc1: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0x04800e92
[   70.881722] mmc1: sdhci: Resp[2]:   0x2fcb8000 | Resp[3]:  0x00000240
[   70.882282] mmc1: sdhci: Host ctl2: 0x0000000b
[   70.886401] mmc1: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x0000007ffffff20c
[   70.893915] ======= mmc1: Tuning windows =======
[   70.893925] mmc1: tuning window[0]: 0x0
[   70.893931] mmc1: tuning window[1]: 0x0
[   70.893937] mmc1: tuning window[2]: 0x0
[   70.893943] mmc1: tuning window[3]: 0x0
[   70.893949] mmc1: tuning window[4]: 0x0
[   70.893954] mmc1: tuning window[5]: 0x0
[   70.893978] mmc1: tuning window[6]: 0x0
[   70.893983] mmc1: tuning window[7]: 0x0
[   70.893988] sdhci: Tap value: 0 | Trim value: 5
[   70.893992] ==================================
[   70.893997] Vendor clock ctrl: 0x500d021
[   70.894002] Vendor SysSW ctrl: 0x38607002
[   70.894007] Vendor Err interrupt status : 0x40000
[   70.894012] Vendor Cap overrides: 0x1107
[   70.894032] Vendor Misc ctrl: 0xffff0080
[   70.894037] Vendor Misc ctrl_1: 0x0
[   70.894042] Vendor Misc ctrl_2: 0x20600000
[   70.894047] Vendor IO trim ctrl: 0x11
[   70.894052] Vendor Tuning ctrl: 0x74024057
[   70.894057] SDMEM comp padctrl: 0x8007007
[   70.894062] Autocal config: 0x20017a00
[   70.894067] Autocal status: 0x1060706
  1. Also, we need you to add similar patch to your rel-32 version software and dump the same register
    so that we can compare the registers. Below patch is for rel-32.

This is L4T32.7.2 dmesg.

[  171.952260] mmc1: Enabling vmmc regulator
[  172.114301] mmc1: host does not support reading read-only switch, assuming write-enable
[  172.252886] mmc1: hw tuning done ...
[  172.252892] ======= mmc1: Tuning windows =======
[  172.253011] mmc1: tuning window[0]: 0xfe00ffff
[  172.253088] mmc1: tuning window[1]: 0x7ffffff
[  172.253168] mmc1: tuning window[2]: 0xfffffff8
[  172.253243] mmc1: tuning window[3]: 0x7fffe01f
[  172.253323] mmc1: tuning window[4]: 0x0
[  172.253392] mmc1: tuning window[5]: 0x0
[  172.253459] mmc1: tuning window[6]: 0x0
[  172.253527] mmc1: tuning window[7]: 0x0
[  172.253597] sdhci: Tap value: 41 | Trim value: 5
[  172.253674] ==================================
[  172.253749] Vendor clock ctrl: 0x529d025
[  172.253816] Vendor SysSW ctrl: 0x38607002
[  172.253889] Vendor Err interrupt status : 0x40000
[  172.253968] Vendor Cap overrides: 0x1107
[  172.254035] Vendor Misc ctrl: 0xffff0098
[  172.254102] Vendor Misc ctrl_1: 0x0
[  172.254326] Vendor Misc ctrl_2: 0x20600000
[  172.254660] Vendor IO trim ctrl: 0x11
[  172.254940] Vendor Tuning ctrl: 0x74024057
[  172.255259] SDMEM comp padctrl: 0x8607000
[  172.255577] Autocal config: 0x20010000
[  172.255862] Autocal status: 0x7060706
[  172.256140] Tuning Status1: 0x3a193a19
[  172.259939] mmc1: new ultra high speed SDR104 SDHC card at address 1234
[  172.260478] mmcblk1: mmc1:1234 SA32G 29.1 GiB
[  172.264365]  mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19

Each full dmesg is here.

202221129_mmc1_error_L4T35.1_tuning_dump_dmesg.txt (95.5 KB)
202221129_mmc1_error_L4T32.7.2_tuning_dump_dmesg.txt (67.6 KB)

Also, please dump me this result on rel-35. Thanks.

cat /sys/kernel/debug/clk/clk_summary

Since there is a difference in sdmmc3 clk before and after SD insertion, I attach both.

[20221130_mmc1_error_L4T35.1_clk_summary_before_inserted_sd.txt]

 osc_div                                                2        2        0    38400000    38400000          0     0  50000
 *[        default_freq                                       0]
...
             sdmmc3                                     0        0        0     3050785      400000          0     0  50000
             *[        default_freq                                       0]

[20221130_mmc1_error_L4T35.1_clk_summary_after_inserted_sd.txt]

 osc_div                                                2        2        0    38400000    38400000          0     0  50000
 *[        default_freq                                       0]
...
             sdmmc3                                     0        0        0   195250195   208000000          0     0  50000
             *[        default_freq                                       0]

20221130_mmc1_error_L4T35.1_clk_summary_before_inserted_sd.txt (58.6 KB)
20221130_mmc1_error_L4T35.1_clk_summary_after_inserted_sd.txt (58.6 KB)

Thanks for sharing. We will check.

please also add this debug print and share log.

--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -1073,6 +1073,8 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
        reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
        sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);

+       pr_err("%s: Dump before running the autocalibration sequence\r\n", mmc_hostname(host->mmc));
+       sdhci_tegra_dumpregs(host);
        udelay(2);
        /* 10 ms timeout */
        ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
@@ -1525,6 +1527,8 @@ static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
        if (tegra_sdhci_skip_retuning(host))
                return 0;

+       pr_err("%s: Dump before running the tuning sequence\r\n", mmc_hostname(host->mmc));
+       sdhci_tegra_dumpregs(reg);
        err = sdhci_execute_tuning(mmc, opcode);
        if (!err && !host->tuning_err)
                tegra_sdhci_post_tuning(host);

Also, please try this patch can fix your issue or not.

--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2806,7 +2806,7 @@ void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)

        /* Wait for Buffer Read Ready interrupt */
        wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
-                          msecs_to_jiffies(800));
+                          msecs_to_jiffies(1000));

 }

please also add this debug print and share log.

20221201_mmc1_error_L4T35.1_tuning_dump_dmesg.txt (101.4 KB)

Also, please try this patch can fix your issue or not.

I applied the patch, but it did not resolve the issue.

Hi,

Please try to remove this from your device tree and see if it resolves issue.

		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;

Thank you for your reply.

I applied your suggestion like this.

[hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-sdhci.dtsi]

	sdmmc3: sdhci@3440000 {
...
#if TEGRA_SDMMC_VERSION >= DT_VERSION_2
		/* nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; */
		/* nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; */
		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
		nvidia,pad-autocal-pull-down-offset-3v3-timeout =
								<0x07>;
# ls -la /proc/device-tree/sdhci@3440000/nvidia\,pad-autocal-pull-*
-r--r--r-- 1 root root 4 12月  2 12:59 /proc/device-tree/sdhci@3440000/nvidia,pad-autocal-pull-down-offset-1v8-timeout
-r--r--r-- 1 root root 4 12月  2 12:59 /proc/device-tree/sdhci@3440000/nvidia,pad-autocal-pull-down-offset-3v3-timeout
-r--r--r-- 1 root root 4 12月  2 12:59 /proc/device-tree/sdhci@3440000/nvidia,pad-autocal-pull-down-offset-sdr104
-r--r--r-- 1 root root 4 12月  2 12:59 /proc/device-tree/sdhci@3440000/nvidia,pad-autocal-pull-up-offset-1v8-timeout
-r--r--r-- 1 root root 4 12月  2 12:59 /proc/device-tree/sdhci@3440000/nvidia,pad-autocal-pull-up-offset-3v3-timeout
-r--r--r-- 1 root root 4 12月  2 12:59 /proc/device-tree/sdhci@3440000/nvidia,pad-autocal-pull-up-offset-sdr104

But it did not resolve the issue.
full dmesg is here.

20221202_mmc1_error_L4T35.1_tuning_dump_dmesg.txt (98.2 KB)

1 Like

Hi,

  1. We see HW tuning is successful now after removing the dt property from #17. Also, I see the card is running at SDR50 which the you claimed was running fine

Are you sure your card was working fine when it is limited to SDR50?

  1. Could you also please take a dump with the following change on top of the debug print of #14. I am suspecting issue with speed mode selection.
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 8ceaaf1..30490ee 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -490,6 +490,7 @@ static void sd_update_bus_speed_mode(struct mmc_card *card)
                    SD_MODE_UHS_SDR12)) {
                        card->sd_bus_speed = UHS_SDR12_BUS_SPEED;
        }
+       pr_info("%s: Card bus speed selected %d\r\n", mmc_hostname(card->host), card->sd_bus_speed);
 }

 static int sd_set_bus_speed_mode(struct mmc_card *card, u8 *status)
@@ -522,6 +523,7 @@ static int sd_set_bus_speed_mode(struct mmc_card *card, u8 *status)
                return 0;
        }

+       pr_info("%s: Card bus timing selected %d\r\n", mmc_hostname(card->host), timing);
        err = mmc_sd_switch(card, 1, 0, card->sd_bus_speed, status);
        if (err)
                return err;
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index acad37a..60bfba3 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -1048,6 +1048,7 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
        if (tegra_platform_is_vsp() || tegra_host->defer_calib)
                return;

+       pr_info("%s: Speed mode timing for setting the auto calibration offsets %d\r\n", mmc_hostname(host->mmc), ios->timing);
        switch (ios->timing) {
        case MMC_TIMING_UHS_SDR104:
                pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
@@ -1073,6 +1074,8 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
        reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
        sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);

+       pr_err("%s: Dump before running the autocalibration sequence\r\n", mmc_hostname(host->mmc));
+       sdhci_tegra_dumpregs(host);
        udelay(2);
        /* 10 ms timeout */
        ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
@@ -1525,6 +1528,8 @@ static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
        if (tegra_sdhci_skip_retuning(host))
                return 0;

+       pr_err("%s: Dump before running the tuning sequence\r\n", mmc_hostname(host->mmc));
+       sdhci_tegra_dumpregs(reg);
        err = sdhci_execute_tuning(mmc, opcode);
        if (!err && !host->tuning_err)
                tegra_sdhci_post_tuning(host);
  1. Need to check if all the required dt properties are present in the your dtb. Could you convert your dtb back to dts and attach it ?

1.Are you sure your card was working fine when it is limited to SDR50?

Yes, when we define uhs-mask=<0x10> and recognized by SDR50, no error has occurred so far.

  1. Could you also please take a dump with the following change on top of the debug print of #14.
    I am suspecting issue with speed mode selection.

I applied patch and got full dmesg.
20221202_2_mmc1_error_L4T35.1_tuning_dump_dmesg.txt (103.9 KB)

  1. Need to check if all the required dt properties are present in the your dtb. Could you convert your dtb back to dts and attach it ?

Convert dtb to dts by following command.

$ dtc -I dtb -O dts -o tegra194-p3668-all-contec.dts tegra194-p3668-all-contec.dtb

tegra194-p3668-all-contec.dts (380.0 KB)

Yes, when we define uhs-mask=<0x10> and recognized by SDR50, no error has occurred so far.

Is this even true after applying so many debug patch added by us?

Could you also add below property to the DT?

“no-sdio”
“no-mmc”

Is this even true after applying so many debug patch added by us?

After applying the patch, we defined uhs-mask=0x10 and confirmed that it is recognized by SDR50.

20221205_mmc1_no_error_L4T35.1_tuning_dump_patch_applied_uhs-mask_0x10_dmesg.txt (103.4 KB)

Could you also add below property to the DT?
“no-sdio”
“no-mmc”

I applied your suggestion, but it did not resolve the issue.

# ls -la /proc/device-tree/sdhci@3440000/* | grep no-
-r--r--r--  1 root root   0 12月  5 14:10 /proc/device-tree/sdhci@3440000/no-mmc
-r--r--r--  1 root root   0 12月  5 14:10 /proc/device-tree/sdhci@3440000/no-sdio

full dmesg is here.
20221205_mmc1_error_L4T35.1_tuning_dump_nosdio_nommc_dmesg.txt (99.4 KB)

Does this log have uhs_mask set or not?

20221205_mmc1_error_L4T35.1_tuning_dump_nosdio_nommc_dmesg.txt