I am trying to implement a hardware level watchdog timer to reset the Jetson Nano when the OS or kernel gets stuck. The watchdog timer is enabled by default according to the documentation. I wrote a script to crash the CPU to test its functionality, but the hardware/jetson nano does not reset when the CPU crashes, and the system remains in the same hung or stuck state. Could you please confirm how I can verify where I might be making mistakes? Are there any example codes, commands, or documentation available to help me learn and implement this correctly? Additionally, please clarify if the jetson nano supports a hardware level watchdog timer. If it does, is it a separate chip, or is it dependent on the main chip/CPU? My goal is to implement an independent watchdog timer that can reset the hardware upon detecting unusual states, such as hangs or stuck conditions at the OS or kernel level. For instance, in microcontrollers, the watchdog timer typically uses a separate oscillator for clock purposes, allowing it to reset the hardware independently when the microcontroller hangs.
Does the Jetson Nano have a similar independent watchdog timer? I read that the Jetson Nano uses the Tegra chip. Could you please explain how the Tegra chip’s watchdog timer works? Specifically
Does the Tegra chip provide a separate clock for the hardware watchdog, or is it dependent on the CPU/processor clock?
How can I configure or test the Tegra chip’s watchdog to ensure it functions as expected in crash scenarios?
The documentation I found on this topic is unclear. If there is no separate hardware for this functionality, would I need to connect an additional microcontroller to achieve it? Please provide a clear and detailed answer.
Thank you for your response regarding the watchdog timer functionality on the jetson nano. While the command echo c > /proc/sysrq-trigger you provided is helpful for testing OS level responses, it does not address several key aspects of my query.
I am specifically looking to understand whether the jetson nano supports a truly independent hardware level watchdog timer that can reset the system in scenarios where the OS or kernel is unresponsive. Is this functionality implemented as a separate hardware Tegra chip, or does it rely on the CPU or OS to function? Additionally, I would like to know whether the Tegra chip’s watchdog timer uses a separate clock source, such as an independent oscillator, or if it is dependent on the processor clock. This detail is crucial for ensuring the watchdog can operate reliably in crash scenarios. I am also seeking guidance on how to configure and test the Tegra chip’s watchdog timer in a way that ensures it functions as intended when the OS or kernel hangs. Are there any example codes, commands, or documentation available to help verify and implement this functionality effectively? Lastly, if the jetson nano does not have a fully independent hardware watchdog timer, would it be necessary to use an external microcontroller such as (STM32, ESP32, PIC18, MSP, NRF) to achieve this level of robustness?
I would appreciate it if you could provide detailed answers or point me to resources that address these specific points comprehensively.
