I tried changing “discontinuous_clk” property in the dtb, but noticed that this property is no where used in the BSP (I might be wrong though, needs confirmation).
If you could let me know which register setting decides between Non-continuous & continuous clock mode, I can dump the register and confirm the current setting too.
Any hints on what could be my issue or where should I focus to fix the issue?
@Rejeesh
What command/tools you are using to grab the sensor image?
If you are using the yavata/v4l2-ctl you can try modify the kernel/drivers/media/platform/tegra/csi/csi2_fops.c
the REG TEGRA_CSI_CIL_PHY_CONTROL from 0xA to 0x4A, you can download the TRM from download center to check the detail.
It might not be the case, since the same sensor with same TX1 side resolution settings (1920x1080) is working in 24.1.
I also tried changing CSI2_PIXEL_STREAM_A_CONTROL0_0 from 0x2A0301F0 to 0x280301F0 (24.1 value , PAD short lines). The output pattern changed but its still not the correct one.
Any other register to look into (specifically related to continuous/ discontinuous mode settings)?