Serial port baud rate is abnormal

chen.xi · September 4, 2025, 8:05am

We used a logic analyzer to automatically obtain the baud rate corresponding to the data sent via the serial port. We found that the baud rate was incorrect. The actual setting was 115200, but the recognized value was 24330.

Use the data sent via cutecom.

The following are the modification information related to the serial port:
dts file:

	bus@0 {
		/* 
		 * serial10 = "/bus@0/serial@810c540000"        UART2
		 * serial5 = "/bus@0/serial@810c510000";        UART5
		 * serial8 = "/bus@0/serial@a808800000";
		 * serial4 = "/bus@0/serial@810c500000";
		 * serial0 = "/bus@0/serial@c5f0000";           UART3(DEBUG)
		 * serial9 = "/bus@0/serial@810c530000";        UART1
 		 */

        serial@810c530000 {     /* UART1 -> SOC_UART9 */
            status = "okay";
        };

        serial@810c540000 {     /* UART2 -> SOC_UART10 */
            status = "okay";
        };

        serial@810c510000 {     /* UART5 -> SOC_UART5 */
            status = "okay";
        };

pinmux file:

			uart5_tx_pj3 {
				nvidia,pins = "uart5_tx_pj3";
				nvidia,function = "uartf_txd";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

			uart5_rx_pj4 {
				nvidia,pins = "uart5_rx_pj4";
				nvidia,function = "uartf_rxd";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

			uart9_tx_pm2 {
				nvidia,pins = "uart9_tx_pm2";
				nvidia,function = "uartj_txd";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

			uart9_rx_pm3 {
				nvidia,pins = "uart9_rx_pm3";
				nvidia,function = "uartj_rxd";
				//nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

			uart10_tx_ph2 {
				nvidia,pins = "uart10_tx_ph2";
				nvidia,function = "uartk_txd";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

			uart10_rx_ph3 {
				nvidia,pins = "uart10_rx_ph3";
				nvidia,function = "uartk_rxd";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

We have found that currently only the debug serial port is functioning properly. UART1, UART2 and UART5 all have this problem.
May I ask if there is any good solution?

KevinFFF · September 4, 2025, 9:27am

Hi chen.xi,

Are you developing the custom carrier boad and using Jetpack 7.0GA for Thor?

Please run the following command to check their clock frequency.

$ sudo cat /sys/kernel/debug/clk/clk_summary|grep serial

chen.xi · September 4, 2025, 9:29am

yes,

nvidia@tegra-ubuntu:~$ cat /etc/nv_tegra_release
# R38 (release), REVISION: 2.0, GCID: 41844464, BOARD: generic, EABI: aarch64, DATE: Fri Aug 22 00:55:42 UTC 2025
# KERNEL_VARIANT: oot
TARGET_USERSPACE_LIB_DIR=nvidia
TARGET_USERSPACE_LIB_DIR_PATH=usr/lib/aarch64-linux-gnu/nvidia
INSTALL_TYPE=openrm

nvidia@tegra-ubuntu:~$ sudo cat /sys/kernel/debug/clk/clk_summary|grep serial
[sudo] password for nvidia:
          pllp_out0                  8       9        0        202500000   0          0     50000      Y            810c540000.serial               apb_pclk
                                                                                                                    810c530000.serial               apb_pclk
                                                                                                                    810c510000.serial               apb_pclk
             uart10                  1       1        0        388675      0          0     50000      Y               810c540000.serial               no_connection_id
             uart9                   1       1        0        388675      0          0     50000      Y               810c530000.serial               no_connection_id
             uart5                   1       1        0        388675      0          0     50000      Y               810c510000.serial               no_connection_id
nvidia@tegra-ubuntu:~$

KevinFFF · September 4, 2025, 9:31am

It seems the current clock frequency is 388675 which results in 388675/16=24292 as baud rate.
I’m checking this with internal and will update to you once I get the result.

chen.xi · September 4, 2025, 10:05am

Looking forward to your reply

KevinFFF · September 5, 2025, 12:39pm

Hi @chen.xi ,

Please apply the following patch to <Linux_for_Tegra>/source/kernel/kernel-noble and rebuild kernel to verify.

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 2b911fd64a12..585e4aed0b09 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2173,11 +2173,15 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 	else
 		clkdiv = 16;
 
-	/*
-	 * Ask the core to calculate the divisor for us.
-	 */
-	baud = uart_get_baud_rate(port, termios, old, 0,
-				  port->uartclk / clkdiv);
+	if (uap->vendor->enable_car) {
+		baud = tty_termios_baud_rate(termios);
+		clk_set_rate(uap->clk, baud * clkdiv);
+	}
+	else {
+		baud = uart_get_baud_rate(port, termios, old, 0,
+					  port->uartclk / clkdiv);
+	}
+
 #ifdef CONFIG_DMA_ENGINE
 	/*
 	 * Adjust RX DMA polling rate with baud rate if not specified.
@@ -2186,10 +2190,12 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 		uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
 #endif
 
-	if (baud > port->uartclk / 16)
-		quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
-	else
-		quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
+	if (!uap->vendor->enable_car) {
+		if (baud > port->uartclk / 16)
+			quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
+		else
+			quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
+	}
 
 	switch (termios->c_cflag & CSIZE) {
 	case CS5:
@@ -2261,22 +2267,23 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 			old_cr &= ~ST_UART011_CR_OVSFACT;
 	}
 
-	/*
-	 * Workaround for the ST Micro oversampling variants to
-	 * increase the bitrate slightly, by lowering the divisor,
-	 * to avoid delayed sampling of start bit at high speeds,
-	 * else we see data corruption.
-	 */
-	if (uap->vendor->oversampling) {
-		if (baud >= 3000000 && baud < 3250000 && quot > 1)
-			quot -= 1;
-		else if (baud > 3250000 && quot > 2)
-			quot -= 2;
+	if (!uap->vendor->enable_car) {
+		/*
+		* Workaround for the ST Micro oversampling variants to
+		* increase the bitrate slightly, by lowering the divisor,
+		* to avoid delayed sampling of start bit at high speeds,
+		* else we see data corruption.
+		*/
+		if (uap->vendor->oversampling) {
+			if (baud >= 3000000 && baud < 3250000 && quot > 1)
+				quot -= 1;
+			else if (baud > 3250000 && quot > 2)
+				quot -= 2;
+		}
+		/* Set baud rate */
+		pl011_write(quot & 0x3f, uap, REG_FBRD);
+		pl011_write(quot >> 6, uap, REG_IBRD);
 	}
-	/* Set baud rate */
-	pl011_write(quot & 0x3f, uap, REG_FBRD);
-	pl011_write(quot >> 6, uap, REG_IBRD);
-
 	/*
 	 * ----------v----------v----------v----------v-----
 	 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
--

chen.xi · September 8, 2025, 1:48am

OK, a test has just been conducted and it has been confirmed that the above patches need to be incorporated into the kernel. The current function is already functioning properly.

Thanks.

ekeechg · September 12, 2025, 7:25am

Hi,Kevin:
Can I config the clk by cmdline?
or is the patch mandatory?

BR//

KevinFFF · September 17, 2025, 1:52am

Hi ekeechg,

This patch is required for using UART on Thor.

system · October 1, 2025, 1:52am

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Serial port baud rate is abnormal

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