Shmoo - memory tool translation

Hi all,

While running the shmoo (Tegra_K1_Memory_CharacterizationV1.0.1) tool I was wondering :

  1. Are all delays written in the result files are shown with respect to the clock (CLK_P/N) ? what is the scale ? (1 ps, 1 ns, register value ?)

  2. Is there a way to know the maximum values tunables of each parameter ? (The purpose is to know if this tool could let us make a more permissive layout than the limits given in the Design Guide ?)

  3. Over temperature/voltage/frequency variations, parameters will “slide” to the right hand side only or it could be to the left too ?

  4. What value should we take in a case like the figure 27 in the shmoo app note ? +/-4 taps margin as close as 0 as possible or the value entered in the top by the tool ? (in this figure is 4 the correct value or 19).
    The figure 29 seems to say to take the widest margin on both side but I’m not sure if it’s for all parameters.


  1. Shmoo test result is excel file, in it are all register values.

  2. You can find the value range by check the bits of each register in AppNote

  3. Mostly that will cause the passed margin to be narrow.

  4. Figure 27 is for 1T or 2T type routing board, as app note said, no need to adjust, if 1T then 4, if 2T then 19.

  5. It says if DliTrimTxDqs is not 0 initially then need to take the widest margin.

Thank you very much.

Okay it confirms I understood it the right way : the widest margin the better.

The title of my topic with “translation” was to know if there is a simple way to find the max delay acceptable for each lane for the layout regarding the max value of the registers ?
Or is it too complex (because all parameters are related to each other) ?

Have a good day,

Memory interface layout rules are contained in OEM design guide, that is the standard of max delay, no need to consider value of register.