Shmoo result DqsIvref

Our custom board could pass sanity test at 792MHz frequency. However, several parameters do not have good margins when running the full shmoo, especially AutocaloffsetDQDQs and DqsIvref. These two results do not have obvious trends on how to adjust the parameters for the next step.

For AutocaloffsetDQDQs, it failed both on the left and right, only two items in the middle passed. For DqsIvref, the margin in the middle is not good, shmoo results did not become better after tuning x axis and y axis.

Below are my questions.

What does DqsIvref mean and which factors on board will influence DqsIvref performance? The +1.35V power current ripple is about 50mv on our board when running full shmoo, would that be the reason of poor DqsIvref result?

In terms of AutocaloffsetDQDQs, does anyone have any suggestions for us to try?

Thanks!

AutocaloffsetDQDQS is for dq dqs pins’ drive strength tuning, if it fails, you will have not enough tuning space for other parameters including DqsIvref, please consider modifying routing/layout of memory part. That is not related to power ripple. You’d better to follow DG to check and redesign the layout, routing, impedance…etc.

Hi Trumany, thanks for your reply.

Under the circumstance, we have to lower the full shmoo target frequency for this version. Below are my extended questions.

  1. Is it correct it could be the target frequency if AutocaloffsetDQDQS could have 4+ taps margin on both side of the x axis setting?

  2. For DqsIvref, which board performance would influence the full shmoo results of this parameter? Is the current ripple of about 50mv on +1.35V power acceptable when running full shmoo?

  3. In shmoo results, it seems the item c950i1300h1000 has the worse results than the other two items. Does that mean there is some instability on VCC_CORE?

Thanks!

4+ taps for AutocaloffsetDQDQS are ‘should be’.

There are many factors that can affect DqsIvref, such as power stability, routing impedance, high frequency signal shielding…etc. Suggest to copy DDR routing from TK1 board. 50mV ripple is less than 5% of 1.35V, should be OK.

No, i don’t think this indicate VCC_CORE unstable, you can check the power plane of VCC_CORE and compare it to TK1 board to see if could do any optimization.

Thank you Trumany for your help. Below are my extended questions.

  1. Supposing the TK1 EVK board is on par, is it correct the memory character performance would be worse if I only make the address signals longer and remain others on EVK board unchanged? Compared with EVK board, our custom board has longer routing on address lines but it is still within the requirements of the design guide.

  2. Currently, the custom board could pass 600MHz full shmoo but do not have enough margin with 792MHz configuration file. I would like to generate the configuration file with higher frequencies such as 692MHz or 712MHz, however, it seems these frequencies are not standard which are not included in the Table 15 and Table 16 on chapter 8 of application note. Is it ok to use configuration file with 712MHz configuration file?

Thanks!

Basically, longer the lines go worse the signals will be, but the more important thing is within the requirements.

You need manually modify the frequency in script to do test if not use exist frequency.