Short and Long scoreboard stall

[njuffa]

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Long scoreboard stall meanings?

Many GPU algorithms are fundamentally limited by the memory resources of the GPU - memory bandwidth and memory latency. Therefore one of the most important stall reasons is Long Scoreboard stall: I was wondering, what is the meaning of this exactly. Like, what is the timeline of an LDG instruction, and is there a way to distinguish long scoreboard stall due to Memory throughput (e.g. L1/L2/gmem throughput) Latency (e.g. cache misses, LG Throttle) Instruction throughput (in case of all memo…

Long cycles on stall_long_sb

I’ve used nsight compute to understand the kernel performance and bottlenecks. The detailed page has pointed to latency issue and wrap stall. The warp state statistics further indicates “stall long scoreboard” (80+ cycles per instruction). I then switched to the source page and sorted the “stall_long_sb” in the navigation. For the first two “stall_long_sb” hot spots, I’ve noticed that both of them don’t involve global memory access. I’ve attached the source code for these two hotspots. Anyone ha…

What are the "long" and "short" scoreboards w.r.t. MIO/L1TEX?