I am optimizing some code on a GF 9600 GT (compute capability 1.1). As per the documentation, coalescing applies for a half-warp only if all threads in the half-warp access contiguous words in sequence and the entire transaction is aligned to the size of the transaction. If not, individual accesses would be issued for each thread. Does this still apply if all threads in the half-warp access the same address? Will this issue 16 accesses to the DDR or just one?