soc_camera strange syncpt failures

I have custom made camera module with AR0330 sensor connected to TK1.
I’ve successfully managed to confiure sensor to required configuration (1080p@30FPS) and get an image out of it.
I can confirm that the signals looks right on oscilloscope, but I am not 100% sure that the sensor really produces the frames at 30Hz (but it should since I’ve followed another ones initialization code).

I am having those syncpt failures (zero registers removed):

[  391.672970] vi vi.0: CSI_A syncpt timeout, syncpt = 180, err = -11
[  391.683950] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000001
[  391.696746] TEGRA_CSI_CSI_CILA_STATUS 0x00010010
[  391.705313] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[  391.717745] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000001
[  391.925095] vi vi.0: CSI_A syncpt timeout, syncpt = 182, err = -11
[  391.933780] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000001
[  391.945749] TEGRA_CSI_CSI_CILA_STATUS 0x00010010
[  391.955139] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[  391.966749] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000001
[  392.179054] vi vi.0: CSI_A syncpt timeout, syncpt = 184, err = -11
[  392.189032] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000001
[  392.195223] TEGRA_CSI_CSI_CILA_STATUS 0x00010010
[  392.200625] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[  392.207011] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000001

There are ~4 failures per second and when I start recording using gstreamer to raw file, there are exactly one frame filled with real image followed by three empty frames each second. This makes me think that even the “valid” frame is not accepted and ends with timeout (it is possible since i can see tears in some frames, like the data are continuously overwriting).

If I am reading those register correctly, there are single bit errors each frame (it is really each frame, since I modified vi2.c to clear errors after read out) and lines are too short (which is also strange because in the captured frame is no missing pixel column).

Could this be problem with CSI-2 bus timing configuration or is there something else to configure?
Thank you for the assistance!

Update: I’ve managed to get rid of “TEGRA_VI_CSI_0_ERROR_STATUS 0x00000001” by modifiing vi2.c, where im_width has not been set for bayer formats. It then worked for a while without any syncpt failures, but after reboot everything (except ERROR_STATUS=0) changed to same state as before… So there is probably something bad with the CSI setup inside AR0330. Are there any requirements for Tegra which could cause the single bit errors?

Following sequence of syncpt errors can be found at the beggining of each streaming

[   97.015858] vi vi.0: MIPI calibration timeout!
[   97.227866] vi vi.0: CSI_A syncpt timeout, syncpt = 2, err = -11
[   97.234897] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000010
[   97.240178] TEGRA_CSI_CSI_CILA_STATUS 0x00040040
[   97.244912] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[   97.250511] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[   97.255531] vi vi.0: Failed to create debugfs directory
[   97.449783] vi vi.0: MIPI calibration timeout!
[   97.655350] vi vi.0: CSI_A syncpt timeout, syncpt = 4, err = -11
[   97.664366] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[   97.670336] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[   97.678627] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[   97.684881] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[   97.689840] vi vi.0: Failed to create debugfs directory
[   98.049995] vi vi.0: CSI_A syncpt timeout, syncpt = 6, err = -11
[   98.057989] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000001
[   98.071959] TEGRA_CSI_CSI_CILA_STATUS 0x00010011
[   98.077057] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[   98.093026] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[   98.303298] vi vi.0: CSI_A syncpt timeout, syncpt = 8, err = -11
[   98.316193] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000001
[   98.327426] TEGRA_CSI_CSI_CILA_STATUS 0x00010010
[   98.338958] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[   98.344693] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000

after then only those single bit errors appears…

For this error you need to make sure the mipi timing is match the spec.