SPE Datasheet

Hello everyone.
I want to access specific memory locations on the SPE domain of AGX Orin, using the Cortex-R5 core. Where can I get the datasheet for the SPE domain?

Thanks in advance.

There is no such specific datasheet. Please refer to TRM for more info. Orin Series SoC Technical Reference Manual

Here in the TRM, its given that the BTCM address is defined in the Global AMAP.
But, in the global AMAP, there is no address mentioned with respect to AON/SPE BTCM or any other AON/SPE addresses.
Please guide me on the usage of TCM in the SPE domain.

Thank you!

BTCM is mapped in SPE firmware, and SPE firmware is running on that.
So you can just follow the SPE firmware guide. No extra action for BTCM function.
Just keep in mind that TCM side is limited, and SPE firmware may not be so complicated though.


Hi ChenJian.

But my application requires to know the start address and the size of the Tightly Coupled Memory (TCM), and this information is unavailable in the TRM. Since, RT applications are time critical, it is best I use the TCM for my code rather any other memory.
Please guide me on this.

Thank you!

Sorry, I don’t catch your point.
What’s application you want to run in SPE?
You can take a look at examples, like GPIO (rt-aux-cpu-demo-fsp/doc/gpio.md).
The GPIO ‘application’ is embedded inside SPE firmware.
I don’t know why ‘application requires to know the start address and the size of the Tightly Coupled Memory (TCM)’.

The SPE firmware is linked with configured script, which make sure the firmware can run correctly in TCM. For example, heap, stack, etc., are allocated in desired blocks.

Please note that DRAM is only for message exchange between SPE and CCPLEX. For those variables in SPE firmware, they are all in TCM by default. Generally, it’s not recommended to access TCM directly through physical address.


Hello ChenJian.
Thank you for the response.
Can I flash a custom firmware onto the Cortex-R5?

Thank you!

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