# SPE gpio enabling **URL:** \ **Category:** Jetson AGX Xavier\ **Tags:** spe\ **Created:** [November 8, 2022, 10:47am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146 "2022-11-08T10:47:08Z")\ **Posts on this page:** 15\ **Page:** 1
**Author:** ![kathiravan](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@kathiravan](https://forums.developer.nvidia.com/u/kathiravan)\ **Post date:** [November 8, 2022, 10:47am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/1 "2022-11-08T10:47:08Z")
In order to access a AON GPIO from the Cortex-R5 SPE/AON for Jetson AGX; the GPIO SCR, GPIO interrupt map and pinmux settings need to be updated as described in below steps. 1. Update SCR values as below in the file `tegra194-mb1-bct-scr-cbb-mini.cfg`: scr.41.6 = 0x18001010; # GPIO\_BB\_SCR\_00\_0 scr.42.6 = 0x18001010; # GPIO\_BB\_SCR\_01\_0 1. Update gpio interrupt mapping as below in `tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg`: gpio-intmap.port.BB.pin.0 = 2; # GPIO BB0 to INT2 gpio-intmap.port.BB.pin.1 = 2; # GPIO BB1 to INT2 1. Update default pinmux configuration as below in the file `tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg`: pinmux.0x0c2f1800 = 0x00000003; # CONFIG BB0 output pinmux.0x0c303040 = 0x0000c004; # can1\_stb\_pbb0 pinmux.0x0c303048 = 0x0000c044; # can1\_en\_pbb1 1. Compile device tree and flash the entire board to ensure that the SCR, gpio interrupt mapping and pinmux settings are flashed on the board. 2. Short GPIO pins of the 40 pin header J30 pin 16 and pin 32, this should print out “GPIO input irq triggered” message since pin 16 is configured as OUT which drives the pin 32 which is configured as INPUT and also has interrupt enabled. i have done above config and replace tx19 spe bin device tree and Image but irq enabled message is not coming . can anyone help me on this ---
**Author:** ![jachen](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jachen/32/14043_2.png) [@jachen](https://forums.developer.nvidia.com/u/jachen)\ **Post date:** [November 9, 2022, 7:42am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/3 "2022-11-09T07:42:41Z")
Hello, Can you use scope to check the pin level when SPE GPIO app is running. Whether the output pin toggles? br ChenJian ---
**Author:** ![kathiravan](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@kathiravan](https://forums.developer.nvidia.com/u/kathiravan)\ **Post date:** [November 10, 2022, 2:14am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/4 "2022-11-10T02:14:26Z")
hi i checked 16th gpio and i am getting .05 voltage and while reading memory of the above registers the value is getting changed comparing with sensor value what we need to right ---
**Author:** ![jachen](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jachen/32/14043_2.png) [@jachen](https://forums.developer.nvidia.com/u/jachen)\ **Post date:** [November 10, 2022, 2:28am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/5 "2022-11-10T02:28:54Z")
Hello, Do you mean that the GPIO cannot output high? Can you also check from kernel side, that GPIO can toggle through sys-FS control? br ChenJian ---
**Author:** ![kathiravan](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@kathiravan](https://forums.developer.nvidia.com/u/kathiravan)\ **Post date:** [November 10, 2022, 5:56am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/7 "2022-11-10T05:56:46Z")
echo 1 \> /sys/class/gpio/PBB.00/value and measured the voltage in 16 pin but value is still 0.05 ---
**Author:** ![kathiravan](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@kathiravan](https://forums.developer.nvidia.com/u/kathiravan)\ **Post date:** [November 10, 2022, 6:59am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/8 "2022-11-10T06:59:36Z")
gpio-313 (PBB.00 |sysfs ) out hi gpio-314 (PBB.01 |sysfs ) in lo after configuring in sysfs able to see the 3.3 in 16th pin. but print is not coming for Device tree as per manual only configured but its not working. 275: 0 0 0 0 gpio 43 Edge 3400000.sdhci cd 276: 2 0 0 0 gpio 77 Edge 15200000.display 277: 0 0 0 0 c360000.pmc 83 Edge sw-wake 278: 0 0 0 0 gpio 36 Edge force-recovery 279: 0 0 0 0 gpio 27 Edge power-key 280: 0 0 0 0 PCI-MSI 134742016 Edge ahci[0001:01:00.0] 281: 0 0 0 0 gpio 149 Edge bluetooth hostwake 282: 1 0 0 0 gpio 119 Edge rt5659 283: 15 0 0 0 gpio 10 Level 1-0008 284: 0 0 0 0 gpio 46 Level tmp451 286: 1 0 0 0 gpio 40 Level 2490000.ethernet:00 288: 0 0 0 0 gpio 9 Edge gpiolib GPIO 314 interrupt also not enabled ---
**Author:** ![jachen](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jachen/32/14043_2.png) [@jachen](https://forums.developer.nvidia.com/u/jachen)\ **Post date:** [November 10, 2022, 7:41am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/9 "2022-11-10T07:41:19Z")
Hello, GPIO test in sys-FS only confirms 1. hardware is good. 2. pins are correct. So in sys-FS, when you configured one pin by output, another pin by input, connect two pins, and changed output pin, you can get the correct value in input side? Let’s confirm this first. Then we can proceed to SPE firmware. 1. Add some print code in GPIO loops, and make sure the app runs as expected. 2. When GPIO output is updated in SPE firmware, check the voltage of output pin, and check whether it toggles as expected. 3. If the interrupt still does not happen, but 2 is good, re-check the configurations in gpio.md, and confirm everything is updated. especially interrupt mapping. It’s better to re-flash the device to make sure the changes are working. br ChenJian ---
**Author:** ![kathiravan](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@kathiravan](https://forums.developer.nvidia.com/u/kathiravan)\ **Post date:** [November 10, 2022, 8:13am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/10 "2022-11-10T08:13:44Z")
> [@jachen](#): > > So in sys-FS, when you configured one pin by output, another pin by input, connect two pins, and changed output pin, you can get the correct value in input side? with above point i done . shorted 16th and 32nd pin and given echo 1 and echo 0 32 pin able to detect the voltage but interrupt is not coming. can you please help me to check how to check interrupt and enable it and how to check SPE is running . steps i follwed for enabling gpio: SPE: 1.set Enable\_gpio=1 in target\_specific.mk in t19x folder 2.build it for t19x target make\_bint19x and replaced the binary in /bootloader. 3.changed pinux config in jetson package. 4.tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg file is not present so where the int register is there i have changed the value. is 4th step is valid . And i am tried to get logs for SPE in serial but unable to do it. is there any way for that if its there please provide me thanks. thanks, kathiravan. ---
**Author:** ![jachen](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jachen/32/14043_2.png) [@jachen](https://forums.developer.nvidia.com/u/jachen)\ **Post date:** [November 11, 2022, 7:16am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/11 "2022-11-11T07:16:48Z")
Hello, For your comment > 4.tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg file is not present so where the int register is there i have changed the value. > > is 4th step is valid . Do you mean you skipped this step? If then, the GPIO interrupt will not map to SPE. Let’s do this one by one. 1. In kernel side, I think you have already verified the GPIO pins are good. 2. BSP part, tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg is in ./bootloader/t186ref/BCT/tegra194-mb1-bct-gpioint-p2888-0000-p2822-0000.cfg 3. You should observe that output pin is toggling if GPIO app is running correctly. For SPE log, please take a look at [Jetson/AGX Xavier Tegra Combined UART - eLinux.org](https://elinux.org/Jetson/AGX_Xavier_Tegra_Combined_UART) SPE: /dev/pts/xx is the port for SPE debug information output. br ChenJian ---
**Author:** ![kathiravan](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@kathiravan](https://forums.developer.nvidia.com/u/kathiravan)\ **Post date:** [November 12, 2022, 1:57pm UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/12 "2022-11-12T13:57:31Z")
hi while i am building spe firmware i am getting spe.bin and replacing the same binary in /bootloader/spe\_t194.bin is that correct. thanks. ---
**Author:** ![jachen](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jachen/32/14043_2.png) [@jachen](https://forums.developer.nvidia.com/u/jachen)\ **Post date:** [November 14, 2022, 1:58am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/13 "2022-11-14T01:58:52Z")
Hello, For SPE firmware compile and flash, you can take a look at l4t-rt/rt-aux-cpu-demo/doc/compile-flash.md, which contains detailed information. I think you should use Xavier AGX (T194), and the built firmware should be l4t-rt/rt-aux-cpu-demo/out/t19x/spe.bin\* br ChenJian ---
**Author:** ![kathiravan](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@kathiravan](https://forums.developer.nvidia.com/u/kathiravan)\ **Post date:** [November 14, 2022, 2:08am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/14 "2022-11-14T02:08:11Z")
hi , i got spe.bin and i replaced the spe.bin in /bootloader/spe\_t194.bin . Is that correct. thanks, kathiravan. ---
**Author:** ![jachen](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jachen/32/14043_2.png) [@jachen](https://forums.developer.nvidia.com/u/jachen)\ **Post date:** [November 14, 2022, 2:12am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/15 "2022-11-14T02:12:36Z")
Hello, It should be good. In addition, you can add some print code in SPE firmware to confirm the new firmware works. br ChenJian ---
**Author:** ![kathiravan](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@kathiravan](https://forums.developer.nvidia.com/u/kathiravan)\ **Post date:** [November 15, 2022, 1:33am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/16 "2022-11-15T01:33:18Z")
Hi , Now i am able to probe 3.3v in 16 pin of agx xavier . thanks for your help :) kathiravan. ---
**Author:** ![system](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/system/32/68080_2.png) [@system](https://forums.developer.nvidia.com/u/system)\ **Post date:** [December 7, 2022, 4:04am UTC](https://forums.developer.nvidia.com/t/spe-gpio-enabling/233146/18 "2022-12-07T04:04:51Z")
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