Specifying L2 cache partition for SM

Accelerated Computing CUDA CUDA Programming and Performance
1

Hello, I have a simple question with l2 cache partition in ampere architecture.
I saw overall ppt of “Dissecting the Ampere GPU Architecture through Microbenchmarking” which was presented in NVIDIA GTC 2021. As far as I understood, it is possible to set a SM to load data from specific partition of L2 cache(Ampere architecutre a100 has 2 partitions of L2 cache).
Can anyone please tell me how to do it or send me a link explaning how to do it?
Or it would be thankful to notify me if i misunderstood the contents of presentation.

Thank you in advance!

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In my view it is generally not possible to direct accesses to one of the two L2 partitions in A100. AFAIK NVIDIA does not publish documentation that describes which accesses will be directed to which partition.

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According to the presentation, the L2 partition alternates every 8 KiB. Based on this, you should be able to infer which partition a given address maps to by measuring access latency from a single SM to each address ( the gap should be around 200 cycles between 2 partitions)

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