Hello folks,
I am facing one issue.
I wish to have the SPI pins enabled on my Jetson board, i.e. spidev.3.0 and spidev.3.1 need to be enabled.
I have followed this link.
https://elinux.org/Jetson/TX2_SPI
I got spidev.3.0 enabled.
I then read this link as well:
However, I am still confused and it doesn’t lead to a proper answer.
Can someone pls let me know as to how can I enable both the SPI on the Jetson TX2 board?
Any directions/ leads will be appreciated.
Thank you,
-Abhishek.
Something like this to enable spidev3.1
spi@3240000{
compatible = "nvidia,tegra186-spi";
reg = <0x0 0x3240000 0x0 0x10000>;
....
....
....
linux,phandle = <0x80>;
spi@0 {
compatible = "spidev";
reg = <0x0>;
spi-max-frequency = <0x1312D00>;
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delau = <0x0>;
};
spi@1 {
compatible = "spidev";
reg = <0x1>;
spi-max-frequency = <0x1312D00>;
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delau = <0x0>;
};
};
Hello all,
This open a /dev/spidev3.1 but it doesn’t work.
What’s your problem. You have to give more detail information otherwise no one can help.
I want to use pin 26th on j21 connector (works like chip select 1). I configured both spi (3240000)
spi@0 {
compatible = “spidev”;
reg = <0x0>;
spi-max-frequency = <0x1312D00>;
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
spi@1 {
compatible = “spidev”;
reg = <0x1>;
spi-max-frequency = <0x1312D00>;
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
I can find into dev both spi’s:
ls /dev/spi
/dev/spidev3.0 /dev/spidev3.1
But when i try to read/write trough spidev3.1 nothing happen. Chip select 1 (26th j21) always is in low level.
Did you probe others pin to check?
No, because this pin must to be root like spi chip select 1.