SPI bus chip select on Jetpack 6.2 with device-tree

[jays]

My device-tree seems to be ok based on a prior post - Overlay preprocessing and macro definitions on Orin Nano for JP6.2

This is on an Jetson Orin Nano running JP 6.4.3 on the dev kit. Pins shown are on the 40 pin header and use spi0 per the device tree.

What I see from this plot is the CS (purple) and the SPI CLKs (orange). Note the SPI clks are all 16 clocks because I’m zoom out in time.

Each division is 200 usec in time. The SPI clock is 3.185 MHz - per the limitation on Jetpack 6.x

Per the controller-data section, should this section be removed completely -
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};

If i have nvidia,enable-hw-bases-cs = 0, then nothing comes out of the spi bus.

I have checked on the other spi chip select on the 40 pin header via spi-dev that it works with multiple bytes and the CS is always asserted low during active SPI clk. This doesn’t seem to be the case with what I had in the device-tree. Again, note the snippet from the link on the other post is from the Feb 14th comment (i.e. in tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi )

Is enable-hw-based-cs causing the problem i see?

[KevinFFF]

Hi jays,

@jays

Is enable-hw-based-cs causing the problem i see?

Could you apply the patch from Jetson orin nano SPI Speed not changing - #9 by KevinFFF to check if it could help with the CS issue you found?

As my understanding, you should specify nvidia,enable-hw-based-cs; option in device tree to enable hardware-based CS.

[jays]

That fixed the problem. Now the CS matches the spi clock.

The next to extend the CS pre and post the SPI clock it looks like there is another set of patches for JP 6.2.

[KevinFFF]

The patch has not been included in any JP6.x release yet.
We are still working on integrating several patches for JP6 and suppose they should be fixed in next Jetpack release.