SPI Chip Select timing issue

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
1

Hi,

I am using SPI to communicate with a device that requires clock idle low (Mode0)
Using a logic analyser I can see that after the data has finished clocking out there is some sort of hold time where the clock and chip select stay low for a while then the clock goes high then the chip select goes high.

The fact that the clock reverts back to high BEFORE the chip select de-asserts is causing issues.

The following command produces this behaviour
sudo ./spidev_test -D /dev/spidev0.0 -s 300 -H

Any ideas as to why this happens?

Thanks

2

Here is a screenshot of the issue - Screenshot-2019-07-16-at-15-15-50 — ImgBB
Top trace is Clock
Bottom trace is Chip Select

from further testing I have also found that after a reboot the clock line stays low after each command, therefore the chip select is valid. It is only after I issue a command that requires clock idle high that the chip select line then always reverts back to high after every command.

I have looked through the driver and cannot find any cause, although it looks like the actual timing is up to the hardware not the driver.

3

Thanks for your report.
May need time to investigate it. Will update to you later.