I am using SPI to communicate with a device that requires clock idle low (Mode0)
Using a logic analyser I can see that after the data has finished clocking out there is some sort of hold time where the clock and chip select stay low for a while then the clock goes high then the chip select goes high.
The fact that the clock reverts back to high BEFORE the chip select de-asserts is causing issues.
The following command produces this behaviour
sudo ./spidev_test -D /dev/spidev0.0 -s 300 -H
Any ideas as to why this happens?