Spi configuration

When I use SPI2_CS0* and SPI2_CS1* as the chip selects for accel and gyro of bmi088, do I need to select SPI1_CS0 or GPIO3_PH.03 for Customer Usage in the pinmux file?

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Also, help to see what is wrong with the device tree I wrote in tegra186-quill-p3310-1000-c03-00-base.dts?

thank you!!

Have reference to below link to configure the PINMUX.
Also have below command to confirm the REG.

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi

https://elinux.org/Jetson/TX2_SPI

  1. When I configure the “cs-gpios” property, the driver does not match the device tree, why?
  2. Where can I see the detailed explanation of this file “tegra_pinctrl_reg”
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  1. Reference to below topic.
    How to set SPI CS(chip select) timing? - #3 by will_lin

  2. Looks like this command didn’t dump SPI1 REG.
    Have check the tegra186-mb1-bct-pinmux-*.cfg to find the SPI1 address and modify it like WIKI and confirm it by devmem2 after boot to the system.

Hello, I checked SPI2_CS0*(G16) and SPI2_CS1*(F16) with devmem2 and the value is 0x8, but the value in pinmux file is 0x408

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pinmux.0x0243d000 = 0x00000408; # gpio_wan8_ph3: rsvd0, pull-up, tristate-disable, input-disable, lpdr-disable
pinmux.0x0243d078 = 0x00000408; # gpio_mdm4_py3: rsvd0, pull-up, tristate-disable, input-disable, lpdr-disable

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Why is this?

Did you modify the cfg file and reflash whole system to apply it?
You can use devmem2 to write the REG to verify the SPI function first.

Yes, I followed the pinmux file shown above, regenerated the .cfg, and reflashed the entire system.
Below is my latest dts file:

&spi0 {
	status = "okay";
	num-cs = <2>;
	cs-gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(H, 3) 0>, <&tegra_main_gpio TEGRA_MAIN_GPIO(Y, 3) 0>;	

	gyro: spidev@0 {
		#address-cell = <0x1>;
		#size-cell = <0x0>;
		compatible = "gyro,bmi08x";
		reg = <0>;	//CS0
		spi-max-frequency = <10000000>;
	
		controller-data {
			nvidia,cs-setup-clk-count = <0x1e>;
			nvidia,cs-hold-clk-count = <0x1e>;
			nvidia,rx-clk-tap-delay = <0x1f>;
			nvidia,tx-clk-tap-delau = <0x0>;
		};
	};

	accel: spidev@1 {
		#address-cell = <0x1>;
		#size-cell = <0x0>;
		compatible = "accel,bmi08x";
		reg = <1>;	//CS1
		spi-max-frequency = <10000000>;
	
		controller-data {
			nvidia,cs-setup-clk-count = <0x1e>;
			nvidia,cs-hold-clk-count = <0x1e>;
			nvidia,rx-clk-tap-delay = <0x1f>;
			nvidia,tx-clk-tap-delau = <0x0>;
		};
	};
};

After that, I changed the “cs-gpios” attribute in the device tree to “cs-gpio”, and then refreshed the device tree. The data read by devmem2 is completely correct, but I don’t know the reason.

How about others PINs like MOSI/MISO/…?
And what’s &spi0 reference to?

The values read by mosi and miso are also consistent with “tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg”;

&spi0 is the “spi0:spi@3210000” node in the “tegra186-soc-spi-dtsi” file

Then the PINs configure should be correct. Could you verify by loopback test.

Thanks, the mosi and miso of this spi cannot be short-circuited at present;

What is the difference between the two properties “cs-gpio” and “cs-gpios”?

In my driver, the return value I get using the following function is -2, i.e. (nb == -2)

int nb = of_gpio_named_count(bmi_dev->np, "cs-gpio");

But the theoretical value should be 2

Should be cs-gpios for GPIO chip select.
Don’t know the cs-gpio for what purpose.

If “cs-gpio=<&tegra_main_gpio TEGRA_MAIN_GPIO(H, 3) 0>, <&tegra_main_gpio TEGRA_MAIN_GPIO(Y, 3) 0>;” is set in the device tree, the read spi2_cs0 and spi2_cs1 are correct, both are 0x408;

If “cs-gpios=<&tegra_main_gpio TEGRA_MAIN_GPIO(H, 3) 0>, <&tegra_main_gpio TEGRA_MAIN_GPIO(Y, 3) 0>;” is set in the device tree, the read spi2_cs0 and spi2_cs1 are wrong, both are 0x8;

I set the node format as follows, the problem is all solved(although not very clear about all the formats of the gpio node)

gpios =<&tegra_main_gpio TEGRA_MAIN_GPIO(H, 3) 0
      &tegra_main_gpio TEGRA_MAIN_GPIO(Y, 3) 0>;

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