The TK1 TRM mentions a bit in the SPI DMA Control Register (SPI_DMA_CTL) called the CONT : Enable Continuous Mode (bit 30). While the TRM doesn’t elaborate on how it works, I assume if that bit is set, the BLOCK_SIZE field in the SPI DMA Block Size (SPI_DMA_BLK) register is ignored and the SPI keeps output-ing (in the case of SPI Master) data as long as the DMA keeps filling the FIFO.
However, I am not seeing this happening. When I setup a DMA to fill the FIFO with the SPI set to Continuous Mode, the DMA seemed to have stopped after moving about 65536 packets to the FIFO. Dumping the SPI Transfer Status register it seemed that the SPI was still in the “Not Ready” state, the DMA bit was still enabled, and SPI interrupt didn’t get triggered and FRAME_END bit wasn’t set, but the SPI FIFO Status showed that the TX_FIFO was full. So it almost seems like SPI is running, but nothing is moving out of the FIFO.
Is SPI Continuous Mode supported on the TK1? If so am I missing something in the setup?
Quick update to this. I re-read the TRM and it does mention “Slave Continuous Mode” so it seem that SPI Continuous Mode would be supported at least for the SPI Slave side of things.
What about for the Master mode? Does the TK1 support Master Continuous Mode?
Furthermore I have managed to set and use the CONT : Enable Continuous Mode (bit 30) in SPI_DMA_CTL for Slave mode SPI. And there it works as expected. It’s only in Master mode I am having the above issue.
OK. Totally understand now! Thanks for your help here.
Is there any way I can know under what restrictions the SPI Master Continuous mode can work. If there are some things I might have to trade off to be able to do SPI Master Continuous mode I am willing to give it a try… I understand that there might be unintended side effects of that, but that’s something I might be able to deal with.
This is the only aspect I am struggling with now and is very critical to our application. I have managed to get this to work on the TX1 easily (also much better documented in the X1 TRM), but we have to support TK1 hardware too.