The TK1 TRM mentions a bit in the SPI DMA Control Register (SPI_DMA_CTL) called the CONT : Enable Continuous Mode (bit 30). While the TRM doesn’t elaborate on how it works, I assume if that bit is set, the BLOCK_SIZE field in the SPI DMA Block Size (SPI_DMA_BLK) register is ignored and the SPI keeps output-ing (in the case of SPI Master) data as long as the DMA keeps filling the FIFO.
However, I am not seeing this happening. When I setup a DMA to fill the FIFO with the SPI set to Continuous Mode, the DMA seemed to have stopped after moving about 65536 packets to the FIFO. Dumping the SPI Transfer Status register it seemed that the SPI was still in the “Not Ready” state, the DMA bit was still enabled, and SPI interrupt didn’t get triggered and FRAME_END bit wasn’t set, but the SPI FIFO Status showed that the TX_FIFO was full. So it almost seems like SPI is running, but nothing is moving out of the FIFO.
Is SPI Continuous Mode supported on the TK1? If so am I missing something in the setup?