SPI GPIO Device Tree 28.1 TX1 to TX2

Hi, all.

I’m having a little trouble moving my SPI configuration from the TX1 to the TX2. I’m confident the SPI device tree elements are set up correctly however, I remember having to do something to the GPIO in the device tree (for the TX1, that I’m not doing in the TX2) as per the guide below:

Configuring SPI in the Device Tree before 28.1 for the TX1 as per this guideline http://elinux.org/Jetson/TX1_SPI suggests making the following change to the device tree for GPIO.

gpio_default: default {
      gpio-to-sfio = <16 17 18 19 20>;
 };

To verify this change (after building and loading the new Device Tree) you follow this guideline http://elinux.org/Jetson/TX1_SPI#Verifying_GPIO_PinMux

This is now seems to be different under 28.1, and now you have to do the following:
File: hardware/nvidia/soc/t210/kernel-dts/tegra210-soc/tegra210-soc-base.dtsi

gpio_default: default{
		gpio-hog;
		function;
			gpios = <TEGRA_GPIO(C, 0) 0 TEGRA_GPIO(C, 1) 0 TEGRA_GPIO(C, 2) 0 TEGRA_GPIO(C, 3) 0 TEGRA_GPIO(C, 4) 0>;
		};

Can someone explain to me if the above is necessary for SPI on the TX2, and if so, how would I make the change as above to the file (hardware/nvidia/soc/t18x/kernel-dts/tegra186-soc/tegra186-soc-base.dtsi). I can’t understand what the values TEGRA_GPIO(C, 0) relate to in the context of SPI.

I liked the guide I mentioned above, because I was able to verify the gpio modification took effect. However, I’m unclear about what the change above actually did…

I’ve been able to successfully have some SPI exchanges between the Jetson + the other embedded solution, however sometimes the other embedded solution won’t transmit back and I’m suspicious the Jetson is doing something with the MISO line (Jetson acting as Master) which is causing conflict.

Many thanks in advance.

The SPI1 pin configure on TX2 is default config as SPI function I think you don’t need add the gpio-hog.
You can dump the pin status by cat /sys/kernel/debug/tegra_gpio to confirm it. The SPI1_xx on TX2 is GPIO_PN3 ~ GPIO_PN6

Hi, ShaneCCC

Yes, SPI is default in the default config, thanks for confirming.

What about an SPI which is not turned on by default, such as SPI2 on the TX2 SOM?

@wachagj
From the pinctrl-tegra186.c this pin config as spi function. You also can check the /sys/kernel/debug/pinctrl/24300000.pinumx/ to know the pin config.

PINGROUP(gpio_sen1_pv1,        SPI2,        RSVD1,        RSVD2,        RSVD3,        0x2050,        1,        Y,	-1,    6,    8,    -1,    10,    11,    12,    N,    -1,    -1,    N),
3336  	PINGROUP(gpio_sen2_pv2,        SPI2,        RSVD1,        RSVD2,        RSVD3,        0x2058,        1,        Y,	-1,    6,    8,    -1,    10,    11,    12,    N,    -1,    -1,    N),
3337  	PINGROUP(gpio_sen3_pv3,        SPI2,        RSVD1,        RSVD2,        RSVD3,        0x2060,        1,        Y,	-1,    6,    8,    -1,    10,    11,    12,    N,    -1,    -1,    N),
3338  	PINGROUP(gpio_sen4_pv4,        SPI2,        RSVD1,        RSVD2,        RSVD3,        0x2068,        1,        Y,	-1,    6,    8,    -1,    10,    11,    12,    N,    -1,    -1,    N),

Thank you! I am experiencing some issues with the SPI2 of the TX2 SOM. I want to communicate over it, I’ve read https://elinux.org/Jetson/TX2_SPI , but when I try to send bytes, no signal change shows on MOSI/CS/SCK.
Based on the source spi-tegra114.c of L4T 28.1, my device tree snippet looks like this:

&spi2{
spidev@0 {
compatible = “spidev”;
reg = <0>;
spi-max-frequency=<25000000>;
/* these were suggested by https://elinux.org/Jetson/TX2_SPI/
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
/
… but from the source code we see that it requires these to be under controller-data */
controller-data {
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};

spidev is built into the kernel, the device nodes exist under /dev.

(I watch the pins E3, E4, F4, F3 of the Jetson TX2 SOM, which is named SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_CS0# but have the functionality of SPI2_SCK SPI2_DIN SPI2_DOUT SPI2_CS0 in the pinmux XLSM)

During boot I see the following SPI related:
[ 1.194936] iommu: Adding device 3210000.spi to group 10
[ 1.200848] iommu: Adding device c260000.spi to group 11
[ 1.206742] iommu: Adding device 3230000.spi to group 12
[ 1.212595] iommu: Adding device 3240000.spi to group 13
[ 2.818872] spi-tegra114 3210000.spi: Prod settings list not initialized
[ 2.819255] spi-tegra114 3210000.spi: Static pin configuration used
[ 2.825991] spi-tegra114 c260000.spi: Static pin configuration used
[ 2.832395] spi-tegra114 3230000.spi: Prod settings list not initialized
[ 2.832707] spi-tegra114 3230000.spi: Static pin configuration used
[ 2.839082] spi-tegra114 3240000.spi: Prod settings list not initialized
[ 2.839423] spi-tegra114 3240000.spi: Static pin configuration used
[ 4.486306] spi-tegra114 3210000.spi: Prod settings list not initialized
[ 4.486454] spi-tegra114 3210000.spi: Static pin configuration used
[ 4.493143] spi-tegra114 3210000.spi: registered master spi0
[ 4.493190] spi spi0.0: setup 8 bpw, ~cpol, ~cpha, 25000000Hz
[ 4.493212] spi spi0.0: setup mode 0, 8 bits/w, 25000000 Hz max --> 0
[ 4.493350] spi-tegra114 3210000.spi: registered child spi0.0
[ 4.521105] spi-tegra114 3230000.spi: Prod settings list not initialized
[ 4.521195] spi-tegra114 3230000.spi: Static pin configuration used
[ 4.527818] spi-tegra114 3230000.spi: registered master spi2
[ 4.527858] spi spi2.0: setup 8 bpw, ~cpol, ~cpha, 25000000Hz
[ 4.527875] spi spi2.0: setup mode 0, 8 bits/w, 25000000 Hz max --> 0
[ 4.527993] spi-tegra114 3230000.spi: registered child spi2.0
[ 4.528054] spi-tegra114 3240000.spi: Prod settings list not initialized
[ 4.528145] spi-tegra114 3240000.spi: Static pin configuration used
[ 4.534749] spi-tegra114 3240000.spi: registered master spi3

I suspect that maybe the “Prod settings list not initialized” could be the culprit, I saw some indicators that these are some vendor specific values for given NVidia devices, however I’ve found no information aboud prod-settings and SPI on Jetson TX2.

What is the linux space name for pins e3,e4,f4,f3?

@asgomez
Check below link to see if help.

https://devtalk.nvidia.com/default/topic/1003613

Sorry but my cuestion is about connector j23. I can work with gpio of j21 and some gpios of j23, but spi0 (phisical pin 38, 340,42,44 pin#: e3,d4,f4,f3, IC Ball Name: GPIO_SEN1, GPIO_SEN2,GPIO_SEN3, GPIO_SEN4) i don’t know how get its number in kernel space.

@asgomez
Those pins for TX2 are SPI function pin only can’t be GPIO pins. You can find the pinumx file to know it.

It is not possible to work like normal GPIO?

Thank you very much.

@asgomez
Yes, can’t be normal GPIO pin.

Ok, i will find another gpio.
Thank you very much @ShaneCCC