SPI interface 6 slaves connected to Expansion Header (J30) on Nvidia Jetson AGX Xavier


I am designing a connector board to connect six of the TI AWR1243 Evaluation Module to the Nvidia Jetson AGX Xavier over SPI interface.

  1. Is it possible to interface 6 slaves connected to SPI1 Expansion Header (J30) on Nvidia Jetson AGX Xavier ?
  2. What is the max length of cable I can use?

Total cable length I need is 30cm
[ Nvidia ] – 15 cm max --> [ Connector board] – 15 cm max – > [ TI board ]

Hi, only 2 CS pins for SPI1 of J30, so only 2 slaves are available. Not sure if the cable is OK, but you can refer to OEM DG which indicates that only up to 125 mm PCB trace is available if you design a custom carrier board.

Hi, Can I use other 4 GPIO pins of J30 as CS to support 6 slave over SPI1 ?

I’am afraid not easy. The two CS are dedicated SFIO pins not GPIO. But if you still want to use other GPIO pins as CS, it depends on if your driver can meet the timing request of slave device.

Hi @harit.shukla, were you able to make this setup working.

I have similar use case where I am trying to interface TI mmware RADAR devices in cascaded mode to capture RAW ADC data over CSI.

Were you also working on to capture RAW ADC data? Can you please let me know what all Nvidia side developments will be required to implement that part?