SPI Interrupt Mask Register

Autonomous Machines Jetson & Embedded Systems Jetson TX1
1

In the TX1 TRM, the SPI Interrupt Mask Register (37.3.13) is confusing. For each bit mentions both.

0 = Enable interrupt …
1 = Disable interrupt …
0 = DISABLE
1 = ENABLE

External Media

So is it 0 to Disable and 1 to Enable? Or?

2

Yes, 0 is to disable, 1 is to enable.

3

Ah OK!

Just to clarify, so setting this bit to 0 will disable the mask, which means it will allow the interrupt to happen. Setting this bit to 1 will enable the mask and hence mask the interrupt!