SPI maximum frequency


I have a Jetson Nano 2GB.
I want to evaluate the maximum data rate of the SPI interfaces of my Jetson Nano 2GB.

I used the following python code, and observed the clock signal of the SPI interface on oscilloscope (pin 23 on the 40-Pin Expansion Header).

In the Jetson Nano datasheet, it is mentioned that the SPI interfaces operate up to 65Mbps, i.e., 65MHz clock signal.
But in my test, any value higher than 25MHz results in a clock frequency of 25MHz.
The result was the same for both SPI0 and SPI1.

Can anyone help me to solve my problem?

Here is my python script:

import time
import spidev

# Enable SPI
spi = spidev.SpiDev()

# Open a connection to a specific bus and device (chip select pin)
spi.open(0, 1)

# Set SPI speed and mode
spi.max_speed_hz = 25000000
spi.mode = 0

while 1:

Check the “spi-max-frequency” in device tree for it.

I know there is a file in /boot/dtb directory named kernel_tegra210-p3448-0003-p3542-0000.dtb

I found the following command to get the spi-max-frequency from the device tree:

fdtget kernel_tegra210-p3448-0003-p3542-0000.dtb spi0 spi-max-frequency


Error at 'spi-max-frequency': FDT_ERR_NOTFOUND

I am newbie in Linux, and don’t exactly know how to manipulate the device tree.
Would you please provide a step-by-step guide about how to change the device tree in in Jetson Nano?


Try dump the device tree by dtc.

sudo apt-get install device-tree-compiler
dtc -I fs -O dts -o extracted.dts /proc/device-tree

I read the contents of the extracted.dts file using vim.
Here is the result:

spi@1 {
                        compatible = "tegra-spidev";
                        reg = <0x1>;
                        spi-max-frequency = <0x1f78a40>;

                        controller-data {
                                nvidia,rx-clk-tap-delay = <0x6>;

                spi@0 {
                        compatible = "tegra-spidev";
                        reg = <0x0>;
                        spi-max-frequency = <0x1f78a40>;

                        controller-data {
                                nvidia,rx-clk-tap-delay = <0x6>;

The HEX number 0x1f78a40 is equal to 33000000 decimal (33MHz).

The …/kernel/kernel-4.9/drivers/spi/spi-tegra114.c SPI host driver.
Looks like the driver limit the max speed to 25MHz

static void tegra_spi_parse_dt(struct tegra_spi_data *tspi)
        const unsigned int *prop;
        struct device_node *np = tspi->dev->of_node;
        struct device_node *nc = NULL;
        struct device_node *found_nc = NULL;
        int len;
        int ret;

        if (of_find_property(np, "nvidia,clock-always-on", NULL))
                tspi->clock_always_on = true;

        if (of_find_property(np, "nvidia,polling-mode", NULL))
                tspi->polling_mode = true;

        if (of_property_read_u32(np, "spi-max-frequency",
                tspi->master->max_speed_hz = 25000000; /* 25MHz */

Where is the directory of this driver?
Does changing that number help to increase the SPI speed?

It’s in kernel driver. You can follow below document to get the source and build it.


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