SPI TPM 2.0 incorrect cs-gpios behavior on Jetson Linux release R35.3.1

We are currently trying to add a TPM module to the NVIDIA Jetson AGX Xavier, but we are not getting the expected CS behavior required for our TPM module.
We use the ST33TPHF2 TPM module, and the driver requires the CS pin to stay low during data transmission. This is implemented in the TPM module by changing the CS state in software (through the cs_change value in the code). This forum post describes the problem we are facing as well: https://forums.developer.nvidia.com/t/spi-infineon-tpm-2-0-cs-gpios-not-correct-work-on-jetpack-5-0-2-and-5-1/243158/9.

We have tried various device tree configurations, but we cannot get the CS pin to work properly. When trying to configure the CS pin in GPIO mode (with cs-gpios), the configured CS pin doesn’t work at all (which is also the case with the linked forum post above). When “nvidia,enable-hw-based-cs” is added, the CS pin works but not with the required behavior for our TPM module. In the image below, the CS pin (blue line) should stay active during the whole transfer until the second clock.

Image from this forum post: https://forums.developer.nvidia.com/t/spi-infineon-tpm-2-0-cs-gpios-not-correct-work-on-jetpack-5-0-2-and-5-1/243158/9

Our device tree configuration for the TPM module is:

spi@3210000 {
      status = "okay";
      cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
      tpm_spi: spi@0{
            status = "okay";
            compatible = "st,st33htpm-spi";
            reg = <0x0>;
            spi-max-frequency = <10000000>; // Based on the datasheet of ST33HTPH2E32AHC0
           controller-data {
                nvidia,rx-clk-tap-delay = <0x11>;

Our connections for the TPM module on the Jetson are:
MISO ↔ pin A56 (PZ.04) in SPI1_DIN mode, input
MOSI ↔ pin D55 (PZ.05) in SPI1_DOUT mode, output
CS ↔ pin E55 (PZ.06) tried in both GPIO3_PZ.06 mode and SPI1_CS0 mode in the pinmux file

We are using the latest NVIDIA Jetson Linux release (R35.3.1, part of Jetpack 5.1.1).
How can we configure the CS pin correctly such that it can be controlled by the TPM driver and thus stays low during the data transmission of the TPM?

Hi user148820,

Are you using the devkit or custom board for AGX Xavier?

Please refer to the following thread to apply a patch for spi driver.
SPI TPM module support fail on jetpack 5.0.2/5.1 on jetson xavier agx - #25 by DaneLLL

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