here is my result.
nvidia@tegra-ubuntu:~$ cat /etc/nv_tegra_release
nvidia@tegra-ubuntu:~$ xxd /proc/device-tree/spi@3210000/status00000000: 6f6b 6179 00 okay.
nvidia@tegra-ubuntu:~$ xxd /proc/device-tree/spi@3210000/spi@0/spi-max-frequency00000000: 01e8 4800 …H.
nvidia@tegra-ubuntu:~$
Hi,
Please check if the nodes are expected:
spi@3210000 { /* SPI1 */
status = "okay";
cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Z, 6) GPIO_ACTIVE_LOW>; /* SPI1_CS0 */
slb9670: spi@0{
compatible = "infineon,slb9670";
reg = <0>;
spi-max-frequency = <32000000>;
status = "okay";
reset-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(A, 2) GPIO_ACTIVE_LOW>; /* GPIO04 */
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x11>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x11>;
};
};
};
To make sure the modification in device tree takes effect. And can compare with device tree in Xavier/Jetpack 4.6 to make sure the setting is identical on the two releases.
the same setting works well on 4.6.0 but 5.0.2
i am sure the flash .dtb is ok
Hi,
On Jetpack 5, certain setting is in dtbo file and probably it is not applied in device tree, so please boot to userspace and run xxd to inspect the device tree. To make sure it is same as Jetpack 4.
Hi,DaneLLL
after build ,We use this dtb
/arch/arm64/boot/dts/nvidia/tegra194-p2888-0001-p2822-0000.dtb
is incorrect?
Did you use /opt/nvidia/jetson-io/jetson-io.py to configure the SPI pins in 40 pin header ?
I config pinmux table
I think maybe the TPM driver on jetpack4.6 can not be used on jetpack 5.0.2 linux kernel
also in<Linux_for_Tegra/bootloader/t186ref/BCT/tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg>
setting :
pinmux.0x0243d040 = 0x00000444; # spi1_sck_pz3: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d020 = 0x00000444; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d058 = 0x00000444; # spi1_mosi_pz5: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d050 = 0x00000448; # spi1_cs1_pz7: rsvd1, pull-up, tristate-enable, input-enable, lpdr-disable
Little confused since you have said using tpm driver from 4.6 in 5.0.2. there is already driver in 5.0.2
We are also using the same tpm and it is working. But when we try to enable both tpm and spidev, in device tree the tpm fails. If we enable only tpm and disable spidev in device tree, then tpm works i.e., will appear as /dev/tpm0
Also please try using jetson-io.py and check. It may do some correct config which might make it work. We used it.
Hi,
Please try the steps in
How to set gpio for spi? - #18 by DaneLLL
To make sure SPI master is working first. And then check TPM driver.
Hi,
Please apply this patch and try again:
spi: tegra: handle cs_change in modes sw_based_cs & cs_gpios · Seeed-Studio/seeed-linux-dtoverlays@1a5db1b · GitHub
Hi DaneLLL ,
[ 15.642437] tpm_tis_spi: probe of spi0.0 failed with error -110
tpm_probe_failed.txt (20.0 KB)
The error code -110 looks similar.
Try to comment the “spi@1” section in the device tree and see whether the /dev/tpm0 appears
Hi sathishkumar,
Can you kindly share your dtsi ?
spi@3210000 { /* SPI1 */
status = "okay";
cs-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Z, 6) GPIO_ACTIVE_LOW>; /* SPI1_CS0 */
slb9670: spi@0{
compatible = "infineon,slb9670";
reg = <0>;
spi-max-frequency = <32000000>;
status = "okay";
reset-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(A, 2) GPIO_ACTIVE_LOW>; /* GPIO04 */
controller-data {
nvidia,variable-length-transfer;
nvidia,rx-clk-tap-delay = <31>;
};
};
/*
spi@1 {
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x11>;
};
};
*/
};
Once a fresh jetpack is installed, we followed the below steps on the Jetson
after configuring the kernel with the following configs
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS_CORE=y
CONFIG_TCG_TIS_SPI=y
run “sudo /opt/nvidia/jetson-io/jetson-io.py” and configure the 40-pin header for SPI1 pins and then save.
use dtc to convert from dtb to dts the dtb file specified in FDT in /boot/extlinux/extlinux.conf
once converted to dts, update the following to the dts file
spi@3210000 {
compatible = "nvidia,tegra186-spi";
reg = <0x00 0x3210000 0x00 0x10000>;
interrupts = <0x00 0x24 0x04>;
#address-cells = <0x01>;
#size-cells = <0x00>;
iommus = <0x02 0x20>;
dma-coherent;
dmas = <0x24 0x0f 0x24 0x0f>;
dma-names = "rx\0tx";
spi-max-frequency = <0x3dfd240>;
nvidia,clk-parents = "pll_p\0clk_m";
clocks = <0x04 0x87 0x04 0x66 0x04 0x0e>;
clock-names = "spi\0pll_p\0clk_m";
resets = <0x04 0x5b>;
reset-names = "spi";
status = "okay";
phandle = <0x2f7>;
prod-settings {
prod_c_cs0 {
prod = <0x04 0xfff 0x11>;
};
};
slb9670@0 {
compatible = "tcg,tpm_tis-spi";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <5000000>;
status = "okay";
controller-data {
nvidia,enable-hw-based-cs;
};
};
/*
spi@1 {
compatible = “tegra-spidev”;
reg = <0x1>;
Hi sathishkumar
than you very much for your reply.
but may I know do your TPM work well on jetpack version 5.0.2/5.1 or just on jetpack4.6.x version ?
because our TPM can works well on jetpack4.6.x but fail on 5.0.2/5.1.
We tried on 5.0.2/5.1 only. We didn’t try on 4.6.x
Hi b-sathishkumar
May I ask whether the TPM you use is SLB9670 or SLB9672?
Or is there a way to measure the behavior of the CS pin?
Because the problem we have is that when we use “nvidia,enable-hw-based-cs”, the behavior of the cs pin is not as required by SLB9672. We have confirmed this with Infineon’s FAE.
The waveforms we measured and the problems we encountered have opened another question on the following website, but no one has answered so far.
Best Regards
Jack Lan
We are using SLB9670
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Hi,
If the SPI device device needs CS pin to be set to cs-gpios, please apply the patch and give it a try:
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 26aa7cb29cbc..20c9799ba448 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -1517,10 +1517,22 @@ static int tegra_spi_transfer_one_message(struct spi_controller *ctrl,
tegra_spi_transfer_delay(xfer->delay_usecs);
}
} else if (xfer->cs_change) {
+ /* CS should de-asserted
+ * at the end of current transfer
+ */
if (cstate && cstate->cs_gpio_valid)
gpio_set_value(spi->cs_gpio, gval);
- tegra_spi_writel(tspi, cmd1, SPI_COMMAND1);
+ if (!tspi->is_hw_based_cs) {
+ u32 cmd1_ncs = (cmd1 & SPI_CS_SW_VAL)
+ ? cmd1 & ~SPI_CS_SW_VAL
+ : cmd1 | SPI_CS_SW_VAL;
+ tegra_spi_writel(tspi, cmd1_ncs, SPI_COMMAND1);
+ }
tegra_spi_transfer_delay(xfer->delay_usecs);
+ /* CS should asserted again for the next transfer */
+ tegra_spi_writel(tspi, cmd1, SPI_COMMAND1);
+ if (cstate && cstate->cs_gpio_valid)
+ gpio_set_value(spi->cs_gpio, !gval);
}
}
@@ -1863,7 +1875,6 @@ static int tegra_spi_probe(struct platform_device *pdev)
tspi = spi_controller_get_devdata(ctrl);
/* the spi->mode bits understood by this driver: */
- ctrl->use_gpio_descriptors = true;
ctrl->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
ctrl->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);