Once a fresh jetpack is installed, we followed the below steps on the Jetson
after configuring the kernel with the following configs
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS_CORE=y
CONFIG_TCG_TIS_SPI=y
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run “sudo /opt/nvidia/jetson-io/jetson-io.py” and configure the 40-pin header for SPI1 pins and then save.
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use dtc to convert from dtb to dts the dtb file specified in FDT in /boot/extlinux/extlinux.conf
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once converted to dts, update the following to the dts file
spi@3210000 { compatible = "nvidia,tegra186-spi"; reg = <0x00 0x3210000 0x00 0x10000>; interrupts = <0x00 0x24 0x04>; #address-cells = <0x01>; #size-cells = <0x00>; iommus = <0x02 0x20>; dma-coherent; dmas = <0x24 0x0f 0x24 0x0f>; dma-names = "rx\0tx"; spi-max-frequency = <0x3dfd240>; nvidia,clk-parents = "pll_p\0clk_m"; clocks = <0x04 0x87 0x04 0x66 0x04 0x0e>; clock-names = "spi\0pll_p\0clk_m"; resets = <0x04 0x5b>; reset-names = "spi"; status = "okay"; phandle = <0x2f7>; prod-settings { prod_c_cs0 { prod = <0x04 0xfff 0x11>; }; }; slb9670@0 { compatible = "tcg,tpm_tis-spi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; spi-max-frequency = <5000000>; status = "okay"; controller-data { nvidia,enable-hw-based-cs; }; };
/*
spi@1 {
compatible = “tegra-spidev”;
reg = <0x1>;
- use dtc again to convert dts to dtb and update the FDT filename in /boot/extlinux/extlinux.conf to the updated dtb file