SPI Transfer Success or not??? Device tree configuration for SPI Controller Correct or not???

Hi All,

The slave device supports only write mode, does not support read mode. After 10 write data, the slave device displays some values. Now I donot have Scope or Bus Analyzers.

Need to confirm that SPI transfer is happening properly or not. How to confirm that SPI transfer is proper using SPI controller registers or some other way.

The device tree values for SPI Master as:

spi@3240000 {
status = “okay”;


            compatible = "driver_name"; 

            reg = <0>;  /* chip select */

    //      spi-max-frequency = <16000000>; 
            spi-max-frequency = <500000>; 
    /*      spi-cpol; 

            status = "okay";

                          //nvidia,cs-setup-clk-count = <0x1e>;




In spi-tegra114.c file, device tree values:


For the above parameters, whether we need to assign values or the default values are enough.

Please confirm.



Attached the timing details image file.

The timing values are:

(VDD - VSS = 2.4V to 3.5V , VDDIO = VDD ,TA = 25°C)
Symbol Parameter Min Typ Max Unit
tcycle Clock Cycle Time 250 - - ns
tAS Address Setup Time 150 - - ns
tAH Address Hold Time 150 - - ns
tCSS Chip Select Setup Time 120 - - ns
tCSH Chip Select Hold Time 60 - - ns
tDSW Write Data Setup Time 50 - - ns
tDHW Write Data Hold Time 15 - - ns
tCLKL Clock Low Time 100 - - ns
tCLKH Clock High Time 100 - - ns
tR Rise Time - - 40 ns
tF Fall Time



  1. It’s hard to confirm it. Only way is to check if any error report from the driver.
  2. Check the …/kernel/kernel-4.4/Documentation/devicetree/bindings/spi/nvidia,spi-tegra114.txt