SPI1_CS1 Removed on TX2?

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

I know the TRM hasn’t been released yet so maybe that will give more information.

But after much headache I discovered that it looks like the SPI1_CS1 pin E13 has been removed and only the SPI1_CS0 pin is available on that bus. :/
I see this noted in “NVIDIA Jetson TX2 OEM Product Design Guide”.

I’m bringing up concern because this is not noted anywhere in the “NVIDIA Jetson TX1 and Jetson TX2 Interface Comparison and Migration” document my team and I have been using to ensure compatibility on our new carrier card.

Can Nvidia chime in as to why this pin was switched to RSVD?

2

I found additional discrepancies not noted in the color coordination.

Pins:
E7 CAM2_MCLK
E8 CAM_VSYNC
A11 JTAG_GP1
C8 BATLOW#

E7 & E8 are not colored Yellow (Not available on Jetson TX1) in the Jetson TX2 OEM Design Guide

C8 is still stated as RSVD in the NVIDIA Jetson TX1 and Jetson TX2 Interface Comparison and Migration document

A11 is not colored Yellow (Not available on Jetson TX1) in the NVIDIA Jetson TX1 and Jetson TX2 Interface Comparison and Migration document.

3

Hi x1tester62, thanks for your findings, these will be fixed in future version, thanks.

4

No problem.
Is there a reason behind the switch of the SPI1_CS1 to RSVD though? Is there any work around?

Looking through it looks like my only option is to bind the chip select signal to a GPIO pin instead of using the discrete SPI1_CS1 pin.

5

It’s due to chip difference. Binding to a GPIO is workable choice.

6

I know this is an old thread but I just ran into this. The pin E13 doesn’t seem to be available in the latest version of the pinmux. If it’s not in the pinmux how do I bind it to a GPIO? I only need it as GPIO, not as a chip select.

James.

7

Hell Sir,

I have a problem because I used SPI1 CS1 (E13) to other SPI slave device in the TX2, but I do not use SPI1_CS1 pin, and this pin always too low.

How do I use it SPI1_CS1 pin ?

SPI1_CS0 pin …> this is okay.
SPI1_CS1 pin …> this is not okay.

SPI1_CLK/MOSI/MISO/CS0 change spi mode, but I do not know CS1 change to SPI_CS1.

    tegra_gpio: gpio@2200000 {
            // HW spi1 (spi3 for SW)
            spi1_enable {
                    status = "okay";
                    label = "enable spi1 function";
                    gpio-hog;
                    function;
                    gpios = <TEGRA_MAIN_GPIO(N, 3) 0 TEGRA_MAIN_GPIO(N, 4) 0 TEGRA_MAIN_GPIO(N, 5) 0 TEGRA_MAIN_GPIO(N, 6) 0>;
            };
    };



    // spi3
    spi@3240000 {
            status = "okay";
            // HW spi1.0 (spi3 for SW)
            spidev@0 {
                    compatible = "spidev";
                    reg = <0>;
                    spi-max-frequency = <25000000>;
                    nvidia,enable-hw-based-cs;
                    nvidia,cs-setup-clk-count = <0x1e>;
                    nvidia,cs-hold-clk-count = <0x1e>;
                    nvidia,rx-clk-tap-delay = <0x1f>;
                    nvidia,tx-clk-tap-delay = <0x0>;
            };

            // HW spi1.1 (spi3 for SW)
            spidev@1 {
                    compatible = "spidev";
                    reg = <1>;
                    spi-max-frequency=<25000000>;
                    nvidia,enable-hw-based-cs;
                    nvidia,cs-setup-clk-count = <0x1e>;
                    nvidia,cs-hold-clk-count = <0x1e>;
                    nvidia,rx-clk-tap-delay = <0x1f>;
                    nvidia,tx-clk-tap-delay = <0x0>;
            };
    };
8

Is the TX2 support SPI1_CS1 (E13) pin controller function?
I tried many methods (e.g. reconfigure pinmix changing… etc), but the SPI1_CS1 (E13) always too low.

SDK version : JetPack 3.3