Hello All,
How to increase the signal strength of SPI signals?
-Thanks.
Hello,
In Xavier TRM, I have seen the below registers:
PADCTL_UART_SPI1_CS0_0
PADCTL_UART_CFG2TMC_SPI1_CS0_0
PADCTL_UART_SPI1_MISO_0
PADCTL_UART_CFG2TMC_SPI1_MISO_0
PADCTL_UART_SPI1_SCK_0
PADCTL_UART_CFG2TMC_SPI1_SCK_0
PADCTL_UART_SPI1_MOSI_0
PADCTL_UART_CFG2TMC_SPI1_MOSI_0
In 2nd registers, CFG_CAL_DRVUP and CFG_CAL_DRVDN fields proper meaning?
i.e. some current value or what is this?
What value, the fields affect the drive strength? Some details are required?
-Thanks.
Hi, do you meet any issue on this? In general, SPI port has no need to tune.
Hello,
In J12 (40 pin header), we used the spi pins. Probed the signals in J12, it looks good.
When we connect the Slave device with cable (10cm length), then the signals are not
good and they looks noise.
-Thanks.
You can search relevant topics in forum for this such as this one: Enable SPI0
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