SPI2 - Jestson AGX orin Not retaining the values which is set in Pinmux

I have a similar problem to the following

my tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi setting

spi2_sck_pcc0 {
	nvidia,pins = "spi2_sck_pcc0";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

spi2_miso_pcc1 {
	nvidia,pins = "spi2_miso_pcc1";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

spi2_mosi_pcc2 {
	nvidia,pins = "spi2_mosi_pcc2";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};


spi2_cs0_pcc3 {
	nvidia,pins = "spi2_cs0_pcc3";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_UP>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

But something wrong with 0x0c302028

root@Jetson:/home/nvidia# busybox devmem 0x0c302048 32
0x00001440
root@Jetson:/home/nvidia# busybox devmem 0x0c302050 32
0x00000440
root@Jetson:/home/nvidia# busybox devmem 0x0c302028 32
0x00000000
root@Jetson:/home/nvidia# busybox devmem 0x0c302038 32
0x00000448
root@Jetson:/home/nvidia#



Try writing the value manually

root@Jetson:/home/nvidia#
root@Jetson:/home/nvidia# busybox devmem 0x0c302028 32 0x00000448
root@Jetson:/home/nvidia# busybox devmem 0x0c302028 32
0x00000448
root@Jetson:/home/nvidia#



Execute normally

root@Jetson:/home/nvidia# spidev_test -s 4000000 -p “\x01\x33” -o spi.out -v -D /dev/spidev1.0
spi mode: 0x0
bits per word: 8
max speed: 4000000 Hz (4000 kHz)
TX | 01 33 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ |.3|
RX | AA AA __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ |…|
root@Jetson:/home/nvidia# spidev_test -s 4000000 -p “\x01\x33” -o spi.out -v -D /dev/spidev1.0
spi mode: 0x0
bits per word: 8
max speed: 4000000 Hz (4000 kHz)
TX | 01 33 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ |.3|
RX | 01 33 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ |.3|
root@Jetson:/home/nvidia#


we flashed by connecting the module in recovery mode and executed

./flash.sh jetson-agx-orin-devkit mmcblk0p1

[flash.log|attachment](upload://agRbtIbzpnM0JLo53AorcVBIrmt.log) (91.9 KB)

Hi channinglan,

Are you using the devkit or custom board for AGX Orin?
What’s your Jetpack version in use?

For 0x0c302028, it is determined by the following node.
Please configure it as the following.

spi2_mosi_pcc2 {
	nvidia,pins = "spi2_mosi_pcc2";
	nvidia,function = "spi2";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
-	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

Do you flash the board to apply the change?

I have the same problem using the jestson-agx-orin evk

root@Jetson:/home/nvidia# cat /etc/nv_tegra_release

R35 (release), REVISION: 4.1, GCID: 33958178, BOARD: t186ref, EABI: aarch64, DATE: Tue Aug 1 19:57:35 UTC 2023

Could you share the steps how you enable spi2 on the AGX Orin devkit?

1.use AGX Orin devkit the steps are the same!

How to set bit 10 SFIO ?
I can’t find it in tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi

Which steps are you referring to ?

If the nvidia,function is configured as spi2, then the bit 10 should be configured as SFIO.

root@Jetson:/home/nvidia# cat /etc/nv_tegra_release

R35 (release), REVISION: 4.1, GCID: 33958178, BOARD: t186ref, EABI: aarch64, DATE: Tue Aug 1 19:57:35 UTC 2023

			spi2_mosi_pcc2 {
				nvidia,pins = "spi2_mosi_pcc2";
				nvidia,function = "spi2";						//PM       1:0  0 spi2
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;			//PUPD     3:2  0 none    1 down 2 up
				nvidia,tristate = <TEGRA_PIN_ENABLE>;			//TRISTATE 4    0 pass    1 tristate
				nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;	//E_IO_HV  5    0 disable 1 enable
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;		//E_INPUT  6    0 disable 1 enable
				nvidia,lpdr = <TEGRA_PIN_ENABLE>;				//E_LPBK   7    0 disable 1 enable
			};

root@Jetson:/home/nvidia# busybox devmem 0x0c302028 32
0x00000120

Test register is not as expected! Unable to set to SPI2!

nvidia,function = “spi2”;

How did you apply the pinmux change?

Please share the full steps how you enable SPI2 on the AGX Orin devkit.

修改
tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
後使用命令 完整更新
./flash.sh jetson-agx-orin-devkit mmcblk0p1

ORIN_EVB_FLASH.log (95.8 KB)

確認
tegra234-mb1-bct-pinmux-p3701-0000-a04_cpp.dts
tegra234-mb1-bct-pinmux-p3701-0000-a04_cpp.dts.txt (49.4 KB)

   spi2_mosi_pcc2 {
    nvidia,pins = "spi2_mosi_pcc2";
    nvidia,function = "spi2";
    nvidia,pull = <0>;
    nvidia,tristate = <0>;
    nvidia,io-high-voltage = <0>;
    nvidia,enable-input = <0>;
    nvidia,lpdr = <0>;
   };

測試 nvidia,function = “spi2”; 這個無法寫入正確的值

root@Jetson:/home/nvidia# busybox devmem 0x0c302028 32
0x00000000

SPI2 is from SPE and I think something else is also configuring this pin.

May I know what’s your use case for SPI2?

1.我也覺得其他地方有設定到
但只有設定到 SPI2_MOSI 很奇怪
其他 SPI2 的暫存器都是正常的,

  1. spi2 將會使用在 spi flash 但目前無設備…故只有量測波形是否正確 , 手動下暫存器 SPI2_MOSI 可以是spidev_test 命令如預期執行