gpio: tegra: fix failed to set the to SFIO
Can't set the GPIO pin to SFIO by device tree.
bug 200549751
Change-Id: Idd331a594cb82b3a5ea4fc47c2784490ff99629f
Signed-off-by: snchen <snchen@nvidia.com>
81/5000
For r32.4.3 EMMC version, I modified kernel GPIO and device tree, but did not modify Uboot and still did not work. Could you please tell me how to use THE SPI function of R32.4.3 EMMC version
Hi, @guoyj@354236533 have you make spi work on r32.4.3 emmc version?
I just follow above steps to enable spi1, but the spi1 sck pin23 keeps high.
Thanks
I just follow above steps to change kernel and device tree, but the spi1 still not work.
The pin23 spi1 sck does not give periodical waveform and keeps high.
tegra_gpio shows
C: 0:2 08 08 08 08 00 00 000000
it's ok
and
cat /proc/device-tree/pinmux@700008d4/common/spi1_sck_pc2/nvidia\,function
it shows spi1
it should be ok too!
The i use devmem2 read 0x70003058, 0xe045 read back.
The register still keeps at value 10 ("rsvd1" not "spi1"),
But sd card nano read back 0xe044, that value represent the register is changed to spi1.
Can device tree change this pin-function correctly on emmc nano? Is there anything i missed?
spi1_sck_pc2 {
nvidia,pins = "spi1_sck_pc2";
- nvidia,function = "rsvd1";
+ nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Using devmem2 can enable spi1 and spi2 by comparing the reg value with sd card version module.
But modifying device tree is more straight, we just hope enable spi through device tree.
Can you give more suggestion?
Thanks
Hi, I am also trying to use the SPI on r32.4.3 eMMC jetson nano. Applying the patch and modifying the device tree were not enough and I did not manage to make it works. @ShaneCCC, jetson-io.py does not seem to work on eMMC version (it just open quickly and close).
Maybe someone knows how devmem2 can be used to enable spi1 and spi2?
sudo ./devmem2 0x70003050 h 0xe044
sudo ./devmem2 0x70003054 h 0xe044
sudo ./devmem2 0x70003058 h 0xe044
sudo ./devmem2 0x7000305c h 0xe048
suod ./devmem2 0x70003060 h 0xe048
you should also apply the gpio kernel patch
and
add something like below maybe unnecessary (i just added it)
spi@7000d400 { /* SPI 1 to 40 pin header */
status = "okay";
I just test spi2 sck pin13, and get waveform from the pin .
sudo ./devmem2 0x6000d004 h 0x0000
sudo ./devmem2 0x70003064 h 0x6044
sudo ./devmem2 0x70003068 h 0x6044
sudo ./devmem2 0x7000306c h 0x6044
sudo ./devmem2 0x70003070 h 0x6048
suod ./devmem2 0x70003074 h 0x6048
Thanks @anhuimain !
I tested for spi2 with your command and it works!! I tested on a custom board where the spi is directly connected to the devices (and not through the 40-pin headers).
I used the patch and could see spi device in /dev/,
but seems the spi speed was abnormal.
when i test with 5M baudrate the data was ok, but when baudrate over than ~5M some data missed.
I use the emmc nano and l4t 32.4.4 with attachment patch. 0001-enable-spi2-device-0-and-no-hw-cs.patch (5.0 KB)
And use spidev_test to have spi loop test, the speed can not reach what i setted.
for example, ./spidev_test -s 8000000, but measured speed was 2000000.
@ShaneCCC
Hi,
looks like the dts spi-max-frequency is useless, printk the value of tspi->master->max_speed_hz read from dts is always 0. So this is the reason why set it in code?
and debug in your driver static int tegra_spi_transfer_one_message(struct spi_master *master, struct spi_message *msg) function, can’t see what happen.
could you help me?
how can i decrease the gap between two transfer msg?