Split PCIe x4 into two PCIe x1 Device Tree

I would like to configure the device tree for a custom carrier board that would enable two mini PCIe 1X slots. I can’t find good refereces / example on what to modify in the device to split the 4x into two 1x.

The Tegra X1 TRM pages 1326-1327 indicate that lanes P1 and P4 can be operated as 1x.

I tried modifying the device as such:

pcie-1 {
		status = "okay";
			nvidia,function = "pcie-x1";
};

 pcie-4 {
 	status = "okay";
    	nvidia,function = "pcie-x1";
};

But this gave me the following errors:

[    0.980558] tegra-pcie 1003000.pcie: failed to get PHY: -19                  
[    0.980596] tegra-pcie 1003000.pcie: failed to get PHYs: -19 

The TX2 and Xavier device trees seem to have a different formatting, so I can’t really translate some of the other forums posts asking similar questions to this.

Hi,

Please refer to TX1 adaptation guide.
Also, x4 port is able to working with x1 device. There is no need to add extra pcie controller in device tree (and such change would not work).

How many pcie port do you want on your board?

I clearly stated I would like two 1X mini PCIe. The adaptation guide was not useful in providing guidance on the making the proper device tree configurations to do this.

The device tree mods i tried to make are not adding a controller they are modifying how the lanes in the existing controller are split.

Hi,

  1. Adaptation guide may not help because Nano has limited capability of uphy configuration and some pins are not open for using.

  2. The device tree mods i tried to make are not adding a controller they are modifying how the lanes in the existing controller are split.

Such method is not supported. Those 4 pins are belonging to one controller. If you modify pcie-4 to pcie-x1, it is like asking the controller to be x1 and x4 simultaneously and would cause error.

Actually, what you want can only be achieved by TX1 or TX2/Xavier but not Nano because of hardware limitation.

Below is uphy lane mapping table from TX1 adaptation guide. You could see there are PCIe x4 + PCIe x1 or PCIe x1 + PCIe x1 usecase. Since lane 0 is occupied by ethernet on Nano module. It is not possible to have 2 x1 pcie ports.