I am designing a custom carrier board. In 2.5.1 of the Nano datasheet, it says the following:
I/O pins cannot be high (>0.5V) before SYS_RESET* goes high. When SYS_RESET* is low, the
maximum voltage applied to any I/O pin is 0.5V. For more information, refer to the Jetson Nano
Product Design Guide.
First off, I cannot find any relevant information in the PDG as the note suggests. Any idea where it is?
Second, I plan on using a buffer for inputs until the system is booted. What all pins need to be buffered? ethernet lines (to Nano)? UART? SPI? I2C?
(nano will be the master device)
I plan to have HDMI_HPD and SYS_EN buffered as well.
I also might have to add HDMI input to the nano. I understand that I need an external device to enable the Nano to receive HDMI input. However, once I decide on how to tackle that, is that essentially another 10+ pins that I will need to buffer?
Hi, please just follow the Design Guide to make custom design and the key point is to follow the power sequence as listed in DG.
I didn’t see anything referring to I/O pins during the power up sequence in the DG. I assume you are talking about “Carrier Board Supplies.” If so, that makes sense for most of our I/O, but we have some connections that go directly to the Nano, not depending on any logic/ICs on the board. Therefore, these components can be transmitting to the Nano before SYS_RESET* is high. These include a USB connection, ethernet lines, and HDMI*. I assume these will have to be buffered.
*(I assume only HDMI_HPD is relevant here, because this pin specifically can be driven high by the display device)
I may also have HDMI input to the Nano. I am not sure what the solution will be, but it may be through PCIE. If that is powered via the same 5V rail that the Nano is, I will have to buffer it I assume.
Any comments on these assumptions? Do I need to buffer all these pins?
Generally no buffer is necessary on USB, ethernet and HDMI, you can check the P3449 schematic in DLC for reference.
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