Supporting a high sampling rate SPI slave triggered on data ready (DRDY) pin

Does anyone have experience developing a Linux SPI driver for a SPI slave device that requires triggering a SPI read based on a DRDY (data ready) pin? I found this stack overflow question (which has some sample code:

I was hoping if anyone could share their experience doing something similar (what sampling rate were you able to achieve), or point to a sample driver in the linux kernel source to serve as reference (seems one of the iio ADC drivers might help)?

i’m hoping to support a device with 10-20KHz sampling rate, is this a realistic goal on a Jetson Nano?

thanks for any tips or stories you may share!

Hi phahn,

Are you using the devkit or custom board for Jetson Nano?
What’s your Jetpack version in use?

Do you want to use Jetson as a SPI-slave device?

Do you mean spi-slave-ready in device tree?

Hi I’m using a custom board, would be using SPI port 1-0. I’m running jetpack4.3.

In my setup the Jetson Nano is running as SPI master and the module I want to connect is a SPI slave. The module has a data ready pin that indicates when a new sample is ready for master to trigger read.

I want to use the tegra210-spi device controller (master, not slave)

It seems a quite old release. Could you update to the latest JP4.6.r(R32.7.4) to verify?

What’s your current driver for SPI master?
You could read the state of spi-slave-ready in your driver and it depends on your use case.


I haven’t written any code yet, I’m just looking for:

  • anyone’s experience with the level of capability that a Linux SPI driver could achieve, specifically how many 10 byte SPI read/write transactions could I trigger per second in a Linux SPI driver, where read/write operations are triggered on a GPIO interrupt (data ready pin)
  • sample code for triggering a SPI transaction based on a DRDY (data ready) signal, either existing in the existing Linux kernel source code drivers or something anyone could share

what does spi-slave-ready refer to specifically?


Maybe you could find if there’s any open source SPI slave driver from GitHub

It is a GPIO connected from SPI slave(Output) to SPI master(Input).
SPI slave will use this GPIO to notify SPI master that it is ready or busy. (i.e. if the SPI slave is in any transaction)

Please refer to the following for details:

- nvidia,slave-ready-gpio: OUT GPIO from slave to report slave status. This
	GPIO, when asserted, implies slave controller is ready for transaction.
	When this GPIO is de-asserted, the master cannot initiate transaction
	with this slave.