SYS_RESET_N in power up and down sequence


I have questions regarding SYS_RESET_N, especially in power up and down sequence.
As documented in Xavier OEM .pdf doc, SYS_RESET_N is a bi-direction signal connected to NRST_IO of PMIC. So, it can be driven from carrier to SoM to reset SoM. And it be can driven from SoM to carrier to reset devices on carrier.

  1. In OEM doc, in the power up sequence diagram, the last step is releasing SYS_RESET_N. Is this driven by SoM (PMIC) which tells carrier that SoM is up? Or is this driven by carrier to reset SoM?
  2. Same in the power down sequence. At the beginning SYS_RESET_N is asserted. Is this driven by SoM (PMIC) to tell carrier that SoM is down? Or is this driven by carrier?
  3. There is also a SYS_RESET_N input on Xavier SoC according to TRM. I am curious how these are connected internally? (SoC(SYS_RESET_N) <— PMIC(NRST_IO) <—> carrier).
    So, when carrier drives SYS_RESET_N on SoM, PMIC will then drives SYS_RESET_N on SoC?


Regarding question 1 and 2, both are from SoM. For question 3, please refer to Power Block Diagram in OEM DG.