TC358743 Interlaced capture?

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
1

Has anyone been able to capture with v4l2 frames of interlaced video? Using the latest driver, I see the timings and format being detected, and I notice my capture settings being set to the same:

[14349.739706] tc358743 7-000f: -----Signal status-----
[14349.739712] tc358743 7-000f: TMDS signal detected: yes
[14349.739718] tc358743 7-000f: Stable sync signal: yes
[14349.739723] tc358743 7-000f: PHY PLL locked: yes
[14349.739729] tc358743 7-000f: PHY DE detected: yes
[14349.749102] tc358743 7-000f: 495:tc358743_get_detected_timings: width 1920 heigh 1080 interlaced 1
[14349.749111] tc358743 7-000f: Detected format: 1920x1080i30.0 (2200x562)
[14349.749118] tc358743 7-000f: horizontal: fp = 0, -sync = 280, bp = 0
[14349.749124] tc358743 7-000f: vertical: fp = 0, -sync = 22, bp = 0
[14349.749130] tc358743 7-000f: vertical bottom field: fp = 0, -sync = 23, bp = 0
[14349.749135] tc358743 7-000f: pixelclock: 37092000
[14349.749140] tc358743 7-000f: flags (0x0):
[14349.749144] tc358743 7-000f: standards (0x0):
[14349.749151] tc358743 7-000f: Configured format: 1920x1080i30.0 (2200x562)
[14349.749155] tc358743 7-000f: horizontal: fp = 0, -sync = 280, bp = 0
[14349.749160] tc358743 7-000f: vertical: fp = 0, -sync = 22, bp = 0
[14349.749165] tc358743 7-000f: vertical bottom field: fp = 0, -sync = 23, bp = 0
[14349.749169] tc358743 7-000f: pixelclock: 37092000
[14349.749173] tc358743 7-000f: flags (0x0):
[14349.749177] tc358743 7-000f: standards (0x0):

But, after setting those in my code, using:

struct v4l2_dv_timings dv = {0};
r = xioctl(fd_video,VIDIOC_QUERY_DV_TIMINGS, &dv);

r = xioctl(fd_video,VIDIOC_S_DV_TIMINGS, &dv);

fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
xioctl(fd_video, VIDIOC_G_FMT, &fmt);

fmt.fmt.pix.field = V4L2_FIELD_ALTERNATE;
//fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_UYVY;
fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_ABGR32;

(I am using ABGR32 since UYVY does not appear to be supported by the TC358743 chip in interlaced mode.

When I create my buffers, I can see they are wrong:

OFFSET: 0, START -1805475840, LENGTH: 8294400

That length corresponds to 1920x1080x4 which would be correct for a full frame.

When I enable detailed csi reporting, I see:

[14518.060494] tc358743 7-000f: Calling tc358743_query_dv_timings
[14518.074711] tc358743 7-000f: 495:tc358743_get_detected_timings: width 1920 heigh 1080 interlaced 1
[14518.074744] tc358743 7-000f: tc358743_query_dv_timings: 1920x1080i30.0 (2200x562)
[14518.074762] tc358743 7-000f: tc358743_query_dv_timings: @@@@@ timings out of range

Over and over and the captured from is green.

Any ideas?

3

hello enc0der,

there’s TX2’s VI driver to have implementation for interlaced sensor modes.
please check L4T sources for reference,
for example,
$L4T_Sources/r32.5/Linux_for_Tegra/source/public/kernel/nvidia/drivers/media/platform/tegra/camera/sensor_common.c

530  	err = read_property_u32(node, "is_interlaced", &value);
531  	if (err)
532  		control->is_interlaced = 0;
533  	else
534  		control->is_interlaced = value;

since Jetson Nano is using VI-2, you may have some implementation for vi2_fops.c
thanks

4

So it looks like the tc358743.c driver does detect interlaced from the decoder:

    bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
            V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;

What I don’t understand it how the CSI-2 ports are setup to work with the interlaced frames. Is that what happens in vi2_fop2.c?

5

hello enc0der,

to clarify,
Jetson Nano and Jetson TX2 were using different VI driver. it’s VI-2 for Nano series, and VI-4 for TX2 series.

it’s TX2’s VI driver to have implementation for interlaced sensor modes but not Nano.
thanks

6

Hey Jerry,

I did understand what you had said, and I went and looked at both source files you mentioned. What wasn’t clear to me is the delineation in how capturing works in the driver. The chip detects interlaced and returns that to the driver when querying the dv_timings.

What I am not 100% sure on is then how that gets used in terms of making changes to the CSI driver to support capturing the frames and how each frame is indicated. I’ve worked with interlaced drivers on other chips before, but I had help on the CSI part of it.

I’m trying to get more detailed documentation from Toshiba at the moment, which will likely help understand what is being sent.

I have a v4l2 driver on another platform that does interlaced capture so I will go take a look at that driver and see how it compares to the one we have right now that works with nano (and only does progressive). (The other platform is a different chip altogether, but does work through CSI)