I have a platform with an external codec connected using I2S on the 40-pins header of the ORIN board.
I’m in TDM mode with the following configuration:
- dsp-a mode
- 48 kHz sample rate
- FSYNC width 0
- ADMAIF2 ↔ I2S2
The big problem I’m facing is that between the I2S controller and the codec I have a couple of level shifters (including the one in the 40-pins header) that are introducing delay on the lines, so that when recording, on the BCLK rising edge on the SOC, I’m sampling the wrong data from the codec (because it is delayed).
Is there any smart solution on the APE side to this kind of issues?
In the TRM I have seen reference to the registers
RX_DATA_OFFSET that I could try to introduce some offsets (maybe that helps?) but it is not specified at which offsets these registers are mapped.