Sorry for replying so late, the priority was little off with this one.
We did some more tests on this, here are some observations.
Here we made a skeleton driver and a matching application. With this combo, we can read/write any register and fill/dump FIFOs inside exar. And during trials on T30, we could see that byte wise fetch from exar RX FIFO fails. As a result, all functions like readb(), memcpy_fromio() etc fails when it is used to read FIFO. (By fails, we mean from a full FIFO, if we read content byte wise , one by one,
The first byte is always copied, but consecutive bytes are lost.). As a result, the only way in which we can access FIFO without data loss is by using readl(), copying 4 bytes at a time. This make sense also, as PCI probably trying to fetch four bytes at once and reporting only one byte. And since this is a FIFO, the read four bytes are popped from FIFO, but three bytes lost forever.
We did the same on an i.MX6 platform. Interestingly, this is different with i.MX6. With i.MX6, we can access FIFOs byte wise and don’t result in data Loss. So we guess this issue is either T30 PCI host hardware not supporting byte wise access, or the host side driver not supporting this access.
We have a intel i210 pcie gigabit ethernet sharing this pci line. This uses IGB driver. We did a check on IGB drivers. IGB driver works without issues on same PCI bus / host driver combo. There we could see all FIFO access is made using readl(). So we think modifying uart driver to use readl() to
fetch from FIFO could solve the issue. We have not tried it though.