tegra-k1 processor PAD , power on reset state

As per datasheet of tegra porocessor, every pad have specific power on reset state (pu,pd,z, etc…).
If pad configured as gpio then we can control its initial state level.
But if pad have dedicated functionality like SPI, I2C, PWM signals,then how to control logic level of that signals.?
Also we have to control logic level of MIPI, USB, Ethernet CLK signals during bootup in bootlalder.so is it possible?

Not very clear about your mean… each interface (SPI, I2C…) has its own driver, no need to control them manually. And also their input voltage is fixed and unchangeable in hardware design.

As per our requirement in bootloader state LVDS ,I2C,SPI,PWM,MIPI,Etheret clock,and USB signals must be at logic low level.
All of this are dedicated pins , so how to control initial power on reset logic level of this signals.?

There is pinmux table in download center, you can refer to it. The POR column shows the power on reset state of each pin, it is unchangeable.