# Tegra K1 USB 3.0 Compliance Test Tools Availability **URL:** \ **Category:** Jetson TK1\ **Created:** [May 24, 2019, 10:50am UTC](https://forums.developer.nvidia.com/t/tegra-k1-usb-3-0-compliance-test-tools-availability/75313 "2019-05-24T10:50:23Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![ankit.patel1](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@ankit.patel1](https://forums.developer.nvidia.com/u/ankit.patel1)\ **Post date:** [May 24, 2019, 10:50am UTC](https://forums.developer.nvidia.com/t/tegra-k1-usb-3-0-compliance-test-tools-availability/75313/1 "2019-05-24T10:50:23Z")
Hello, We have the document “TegraK1\_USB2.0\_Compliance\_Test\_AppNote\_DA0719007.pdf” for USB 2.0 compliance testing.(Test J, Test K pattern) Is there any reference or tool for the USB 3.0 compliance test procedure for TK1. Regards, Ankit ---
**Author:** ![Trumany](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/trumany/32/14043_2.png) [@Trumany](https://forums.developer.nvidia.com/u/Trumany)\ **Post date:** [May 27, 2019, 3:45am UTC](https://forums.developer.nvidia.com/t/tegra-k1-usb-3-0-compliance-test-tools-availability/75313/2 "2019-05-27T03:45:02Z")
Hi, you can try below steps: 1. Before test, the power control settings need to be ON in order to prevent USB xHCI controller from going to sleep during the test. From the shell, enter the following commands. echo on \> /sys/bus/usb/devices/usb1/power/control echo on \> /sys/bus/usb/devices/usb2/power/control 2. The compliance registers must be set after USB 3.0 test fixture connected to Tegra, checking registers as below. T\_XUSB\_XHCI\_OP\_PORTSC[8:5] = Ah (TX)/ 05h (RX) T\_XUSB\_XHCI\_EC\_DBCAP\_DCPORTSC[8:5] =Ah (TX)/ 05h (RX) You can refer to the doc of TX1 and TK1 TRM for register address and other procedure setting: [url][https://developer.nvidia.com/embedded/dlc/tx1-usbss-compliance[/url]](https://developer.nvidia.com/embedded/dlc/tx1-usbss-compliance%5B/url%5D) ---
**Author:** ![ankit.patel1](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@ankit.patel1](https://forums.developer.nvidia.com/u/ankit.patel1)\ **Post date:** [May 28, 2019, 4:47am UTC](https://forums.developer.nvidia.com/t/tegra-k1-usb-3-0-compliance-test-tools-availability/75313/3 "2019-05-28T04:47:53Z")
Hi, Thanks for the inputs. I think as per your inputs USB3.0 Host Test Fixture hardware is required right? I am looking for the same solution like [url][https://devtalk.nvidia.com/default/topic/1008479/jetson-tx1/how-specify-xusb-register-address/1[/url]](https://devtalk.nvidia.com/default/topic/1008479/jetson-tx1/how-specify-xusb-register-address/1%5B/url%5D) This is to test electrical compliance test(TEST\_J,TEST\_K etc.) for USB 2.0 I want to test electrical compliance test for USB 3.0(CP0 or CP1 etc.) Do you have any idea on that? Regards, Ankit ---
**Author:** ![ankit.patel1](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@ankit.patel1](https://forums.developer.nvidia.com/u/ankit.patel1)\ **Post date:** [May 31, 2019, 12:27pm UTC](https://forums.developer.nvidia.com/t/tegra-k1-usb-3-0-compliance-test-tools-availability/75313/4 "2019-05-31T12:27:21Z")
> [@Trumany](#): > > Hi, you can try below steps: > > 1. Before test, the power control settings need to be ON in order to prevent USB xHCI controller from going to sleep during the test. From the shell, enter the following commands. > echo on \> /sys/bus/usb/devices/usb1/power/control > echo on \> /sys/bus/usb/devices/usb2/power/control > > 2. The compliance registers must be set after USB 3.0 test fixture connected to Tegra, checking registers as below. > T\_XUSB\_XHCI\_OP\_PORTSC[8:5] = Ah (TX)/ 05h (RX) > T\_XUSB\_XHCI\_EC\_DBCAP\_DCPORTSC[8:5] =Ah (TX)/ 05h (RX) > > You can refer to the doc of TX1 and TK1 TRM for register address and other procedure setting: [https://developer.nvidia.com/embedded/dlc/tx1-usbss-compliance](https://developer.nvidia.com/embedded/dlc/tx1-usbss-compliance) I cannot set T\_XUSB\_XHCI\_OP\_PORTSC(0x70090420) = 0x0A. “devmem2 0x70090420 w 0x10340” command executed successfully, but when i read back the register “0x70090420” , it is returtned “0x2A0”. Is there any other register need to set before this? Regards, Ankit ---
**Author:** ![ankit.patel1](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@ankit.patel1](https://forums.developer.nvidia.com/u/ankit.patel1)\ **Post date:** [June 3, 2019, 10:33am UTC](https://forums.developer.nvidia.com/t/tegra-k1-usb-3-0-compliance-test-tools-availability/75313/5 "2019-06-03T10:33:58Z")
Hello, Is there any updates on this? Regards, Ankit ---
**Author:** ![Trumany](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/trumany/32/14043_2.png) [@Trumany](https://forums.developer.nvidia.com/u/Trumany)\ **Post date:** [June 14, 2019, 6:13am UTC](https://forums.developer.nvidia.com/t/tegra-k1-usb-3-0-compliance-test-tools-availability/75313/6 "2019-06-14T06:13:43Z")
We are checking internally, will feedback once available, thanks.