I am trying to root my newly built customized board based on Jetson TK1. Neither I am unable to enter the recovery mode nor I see any prints on console.
What will be the the possible reasons for that ?
I have checked all the powers and clocks. According to TegraK1_Embedded_DG_v03 page no 14 table no 8 Recommended states for Tegra power rails ; the powers that are needed to be on in early power on stage are fine.
The table can be seen in the attached picture.
Please make sure the power sequence is correct as listed in chapter Power Sequencing in DG. Also there is Design Checklists in it which should be followed well too.
We have checked the power on sequence on our board and deduced following observations:
The delay in power up sequence between different powers is four times of the expected delay. e.g +VDD_CORE should be powered on 1ms after +1.05V_LPO_VDD_RTC, however in our case, this delay is 4ms.
The sequences are correct, however the only exception in sequence is +3.3V_LPO, which is powered on after +1.35V_LPO but according to power up sequence, it should be powered up before it.
Attached is the sequence that we have observed using oscilloscope. The highlighted power is not as expected.
Actual power sequence that is mentioned in the design guide is as follows
Please check your design and compare to reference to find out why the sequence is different to guide. And change design to meet the request then.
Can you please confirm whether the change in sequence is the problem or timing is the issue since this power sequence in being followed by PMIC (AS3722) which is already programmed?
You can check the reference schematic to find out the control signals of power rails.
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