Tegra TK1 PCB Routing Guide

I have read the DDR Design guide for routing but we are getting the problem that we are unable too meet those requirements for Data bus.
according to design guide, maximum length for data line is about 33.34mm but in our case we can route it to 38.4 mm. and i have routed 2 bytes per layer.
we have matched the length of every byte to 0mm. there is not length difference in the signals of Byte.
and Address signals are according to design guide.
If we proceed with this confugration, at what speed we can use our DDR.
our Board is 16 layer board and i am attaching the stack up of our board.
stackup.xlsx (9.79 KB)

Hi, your design should be follow the guide strictly, otherwise we can’t guarantee the performance. The potential issue of violating guide is hard to confirm, it can be speed or unstable or even fail to power on system.